List of Figures

| Table of Contents | List of Figures | List of Tables |

Figure 1-1. Everest Functional Block Diagram

Figure 1-2. IO4 Functional Block Diagram

Figure 1-3. Everest System Buses

Figure 1-4. Everest Buses and Interface ASICs

Figure 1-5. Polled Serial Bus

Figure 1-6. SCSI Drive Addressing

Figure 2-1. Everest Bus Parity Checkpoints

Figure 2-2. IP19 Board Error Detection Logic

Figure 2-3. IP19 Board Component Locations

Figure 2-4. IP21 Board Error Detection Logic

Figure 2-5. IP21 Board Component Placement

Figure 2-6. IO4/VCAM Board Error Detection Logic

Figure 2-7. IO4/VCAM Component Locations

Figure 2-8. MC3 Memory Board Error Detection Logic

Figure 2-9. MC3 Board Component Locations

Figure 2-10. MC3 SIMM Bank and Leaf Organization

Figure 3-1. Power Subsystem Block Diagram

Figure 3-2. Rackmount and Deskside Status Panel and OLS Power and Fault Indicators

Figure 3-3. IP19 and IP21 Board Power Fault Indicators and Power Brick Locations

Figure 3-4. MC3 Board Fault Indicator and Power Brick Locations

Figure 3-5. First IO4 Board/VCAM Fault Indicator and Voltage Regulator Locations

Figure 3-6. Remote VCAM Fault Indicator and Voltage Regulator Locations

Figure 3-7. F Mezzanine Board Fault Indicator and Voltage Regulator Locations

Figure 3-8. Power Board Fault LEDs

Figure 3-9. SCSIBox Fault Indicators

Figure 3-10. Power OK (POKx) Signals

Figure 3-11. Power-On Sequence (Part 1 of 2)

Figure 3-12. Power-On Sequence (Part 2 of 2)

Figure 3-13. Power-On Signal Timing

Figure 3-14. System Controller Voltage Status Menu

Figure 3-15. Power Subsystem Voltage Monitoring

Figure 4-1. System Controller Input/Output Signals

Figure 4-2. Deskside System Controller Sensors

Figure 4-3. Rackmount System Controller Sensors

Figure 4-4. System Status Panel (Deskside and Rackmount Versions)

Figure 4-5. System Controller Menus: Key switch On

Figure 4-6. System Controller Menus: Manager Position

Figure 4-7. System Controller Menus: Debug Settings

Figure 5-1. IP19 Power-On Test Sequence (Part 1 of 4)

Figure 5-2. Power-On Test Sequence (Part 2 of 4)

Figure 5-3. Power-On Test Sequence (Part 3 of 4)

Figure 5-4. Power-On Test Sequence (Part 4 of 4)

Figure 5-5. IP21 Power-On Test Sequence (1 of 4)

Figure 5-6. IP21 Power-On Test Sequence (2 of 4)

Figure 5-7. IP21 Power-On Test Sequence (3 of 4)

Figure 5-8. IP21 Power-On Test Sequence (4 of 4)

Figure 5-9. CPU Board Fault Indicators (IP19 Shown)

Figure 5-10. Slave Processor LED Pattern

Figure 5-11. CPU LED Pattern when Polling