Chapter 6. Interactive Diagnostics Environment (IDE)

Chapter 6. Interactive Diagnostics Environment (IDE)
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Overview

This chapter describes the Everest board tests that are presently supported by the interactive diagnostics environment (IDE) and explains the various types of error messages.

Available IDE Tests

The general sets of IDE tests are:

IO4 tests, described in Section 6.3, "IO4 IDE Tests"
IP19 tests, described in Section 6.4, "IP19 IDE Tests"
MC3 tests, described in Section 6.5, "MC3 IDE Tests"

Error message syntax is described in Section 2.6, "Error Message Syntax."

Note: At the time this guide went to press for the -030 revision, the IP21 IDE diagnostics were not available.

The following section describes the steps to run an IDE test.

Running an IDE Test

The steps to run an IDE test are:

Shut the system down (if it is not shut down already).
Run diagnostics by selecting option 3 (Run Diagnostics) from the startup screen, or by using the Command Monitor to boot /stand/ide.
Set the desired test level. By changing the test level, you can see varying amounts of detail as each test runs. To set a report level, enter
report=N
In the above command, N is the desired report level (1-5). The available test levels and the default test levels are described in the specific board-test sections.
Select the appropriate testing modes. The different testing modes change the way that the tests run. Not all modes are available for all tests. For example, to enable quickmode, enter
setenv quickmode 1
See the specific board-test section for available modes.
Run the specific test. For example, to check all memory addresses to see if they are writable, type the following:
mem4
Interpret the results and either take action to correct the problem or run more tests to obtain more information.

IO4 IDE Tests

The IO4 IDE tests are divided into four categories:

IO4 interface tests, described in Section 6.3.1, "IO4 Interface."
SCSI adapter tests, described in Section 6.3.2, "VME Adapter."
VME adapter tests, described in Section 6.3.3, "SCSI Adapter."
Everest peripheral controller (EPC) tests, described in Section 6.3.4, "Everest Peripheral Controller (EPC)."

To start an IO4 IDE test, boot IDE from the Command Monitor. See Section 6.2, "Running an IDE Test."

Set the desired report level. The default report level is 2.

Available report levels are shown in Table 6-1

Table 6-1. IO4 IDE Report Levels

Report Level	Function	Comments
Level 5	Displays debugging messages.	Too much detail for most testing scenarios.
Level 4	Prints out memory locations as they are written.	Increases testing time.
Level 3	Prints out one-line functional descriptions within tests.	Probably the most useful level for general testing.
Level 2 (default)	Prints out only errors and titles.	This is the default level.
Level 1	Prints out only titles and pass/fail.

Each test level prints out messages for that level and all lower levels.

After setting the report level, choose a test mode (if desired). The following modes are available:

quickmode

Runs the tests slightly faster than usual. Note that currently there is little difference in testing time with quickmode enabled.

To enable quickmode, enter

setenv quickmode 1

To disable quickmode, enter

unsetenv quickmode

continue-on-error

Normally, IO4 tests stop after the first error. Enabling continue-on-error mode causes the tests to continue even after an error is encountered.

To enable continue-on-error mode, enter

setenv cont_on_error 1

To disable continue-on-error mode, enter

unsetenv cont_on_error

By default, continue-on-error mode is enabled for most of the tests.

io_all

The io_all command runs all tests that

work properly
work reliably
do not require any operator intervention to run

This command does not run any IO4 tests that are not completely functional, that are not known to be completely reliable, and that require the operator to interpret the results.

To use io_all, enter

io_all

IO4 Interface

Table 6-2 shows the tests available for the IO4 interface.

Table 6-2. IO4 Interface Tests

Test	Function	Description
check_iocfg	Checks the IO4 configuration against the nonvolatile RAM (NVRAM)	Compares the actual setup of the IO4 board to the values specified in the NVRAM. Each IO4 board in the system is checked to see that it has all the adapters specified in the NVRAM and that they are of the specified types. If `report` is set to `VERBOSE`, the test prints configuration information about each board even if no errors are encountered.
io4_regtest	Read/write test of IO4 registers	Tests the following registers: IO4_CONF_LW IO4_CONF_SW IO4_CONF_ADAP IO4_CONF_INTRVECTOR IO4_CONF_GFXCOMMAND IO4_CONF_ETIMEOUT IO4_CONF_RTIMEOUT IO4_CONF_INTRMASK Although these are not the only IO4 registers, they are the only ones that can be safely checked with the read/write test.
io4_pioerr	IO4 PIO bus error test	Tries to generate an error interrupt by attempting to write to IO4 adapter 0 (which does not exist). This tests the capability of the IO4 board to generate errors and tests the path between the IO4 board and the IP19 or IP21 board.
mapram_test	Read/write test of IO4 map RAM	Tests the IO4 mapping RAM as a small memory array. Tests memory with pattern read/write, address-in-address, and marching 1's test patterns.
check_hinv	Checks type of board in each slot	Prints out locations and types of all boards currently installed in the system.

VME Adapter

Table 6-3 lists the VME adapter tests

Table 6-3. IO4 VME Adapter Tests

Test	Function	Description
fregs	Test the VMECC F chip	Checks version number for correctness. Performs read/write tests on the following registers: FCHIP_VERSION_NUMBER FCHIP_MASTER_ID FCHIP_INTR_MAP FCHIP_FIFO_DEPTH FCHIP_FCI_ERROR_CMND FCHIP_TLB_BASE FCHIP_ORDER_READ_RESP FCHIP_DMA_TIMEOUT FCHIP_INTR_MASK FCHIP_INTR_SET_MASK FCHIP_INTR_RESET_MASK FCHIP_SW_FCI_RESET FCHIP_IBUS_ERROR_CMND FCHIP_TLB_FLUSH FCHIP_ERROR FCHIP_ERROR_CLEAR FCHIP_TLB_IO0 FCHIP_TLB_IO1 FCHIP_TLB_IO2 FCHIP_TLB_IO3 FCHIP_TLB_IO4 FCHIP_TLB_IO5 FCHIP_TLB_IO6 FCHIP_TLB_IO7 FCHIP_TLB_EBUS0 FCHIP_TLB_EBUS1 FCHIP_TLB_EBUS2 FCHIP_TLB_EBUS3 FCHIP_TLB_EBUS4 FCHIP_TLB_EBUS5 FCHIP_TLB_EBUS6 FCHIP_TLB_EBUS7. A large window register test, address line test, interrupt test and a test of the ERROR register is then performed.
vmeregs	Test the VMECC registers	Performs a register test on the following vmecc registers: VMECC_RMWMASK VMECC_RMWSET VMECC_RMWADDR VMECC_RMWAM VMECC_RMWTRIG VMECC_ERRADDRVME VMECC_ERRXTRAVME VMECC_ERRORCAUSES VMECC_ERRCAUSECLR VMECC_DMAVADDR VMECC_DMAEADDR VMECC_DMABCNT VMECC_DMAPARMS VMECC_CONFIG VMECC_A64SLVMATCH VMECC_A64MASTER VMECC_VECTORERROR VMECC_VECTORIRQ1 VMECC_VECTORIRQ2 VMECC_VECTORIRQ3 VMECC_VECTORIRQ4 VMECC_VECTORIRQ5 VMECC_VECTORIRQ6 VMECC_VECTORIRQ7 VMECC_VECTORDMAENG VMECC_VECTORAUX0 VMECC_VECTORAUX1 VMECC_IACK1 VMECC_IACK2 VMECC_IACK3 VMECC_IACK4 VMECC_IACK5 VMECC_IACK6 VMECC_IACK7 VMECC_INT_ENABLE VMECC_INT_REQUESTSM VMECC_INT_ENABLESET VMECC_INT_ENABLECLR VMECC_PIOTIMER An address test of the vmecc it then executed.
vmeintr	Test the VMECC self interrupts	This test installs an interrupt handler, then generates a vmecc interrupt. The occurrence of this interrupt is checked for and then the execution of the correct interrupt handler is checked for.
vmeberr	Test for VMECC bus errors	This test generates bus errors by disabling one of the slave address spaces and doing an access to the disabled area. No response should be returned, generating a bus error interrupt.
vmelpbk	Test the VMECC loopback capability	This test performs VME accesses in A24 PIO Loopback mode and A32 PIO Loopback Mode. Halfword accesses and word accesses are tested for each of these cases.
cddata	Test the cdsio interrupts	The cdsio loopbacks are performed at several different baud rates. The received data from the loopback is tested for accuracy. The status bits from the serial port are tested for framing, overrun and parity errors. This test can be run with internal loopback or with an external loopback plug.
cdintr	Test the cdsio interrupts	This test transmits a byte to the serial port in internal loopback mode. The test then waits for an interrupt or a time out condition to occur.
vmedata	Test the VMEcc DMA engine	This test checks the VME DMA engine using the cdsio as the external controller. The DMA engine in VMECC is used to transfer data from host memory to controller memory and vice-versa.

SCSI Adapter

Table 6-4 lists the IO4 SCSI adapter tests

Table 6-4. IO4 SCSI Adapter Tests

Test	Function	Description
S1_regtest	Read/write test for the S1 chip registers	Tests and performs address-in-address testing for the following S1 chip registers: S1_INTF_R_SEQ_REGS 0 - 0xF S1_INTF_R_OP_BR_0 S1_INTF_R_OP_BR_1 S1_INTF_W_SEQ_REGS 0 - 0xF S1_INTF_W_OP_BR_0 S1_INTF_W_OP_BR_1 A total of 36 registers are tested. Although the registers listed above are not the only S1 registers, they are the only ones that may be used safely by the read/write tests.
regs_95a	Read/write test for WD95A SCSI adapter chip registers	TBD; test is still being developed
scsi_intr	SCSI interrupt test	TBD; test under development
scsi_selftest	SCSI device self-test	TBD; test under development
scsi_dma	SCSI DMA error-generation test	TBD; test under development

Everest Peripheral Controller (EPC)

Table 6-5 lists tests for the Everest peripheral controller (EPC) on the IO 4 board

Table 6-5. Everest Peripheral Controller (EPC) Tests

Test	Function	Description
epc_regtest	Read/write test for EPC chip registers.	Performs basic read/write tests on EPC chip registers, including the parallel port registers. Tests the following registers: EPC_IIDDUART0 EPC_IIDDUART1 EPC_IIDENET EPC_IIDPROFTIM EPC_IIDSPARE EPC_IIDPPORT EPC_IIDERROR EPC_EADDR[0-5] EPC_TCMD EPC_RCMD EPC_TBASELO EPC_TBASEHI EPC_TLIMIT EPC_TTOP EPC_TITIMER EPC_RBASELO EPC_RBASEHI EPC_RLIMIT EPC_RTOP EPC_RITIMER EPC_PPBASELO EPC_PPBASEHI EPC_PPLEN EPC_PPCTRL This is a good basic test for the parallel port. For a more thorough testing a test fixture is required.
epc_nvram	Read/write test for EPC NVRAM	Performs a read/write pattern and address-in-address testing for all the NVRAM accessible to the EPC chip. Although the NVRAM is physically on the real-time clock (RTC) chip, it occupies a separate address space and is accessed differently, and thus requires a separate test.
epc_rtcreg	Read/write test for the real-time clock (RTC) chip and NVRAM	Tests the RTC registers and a small amount of NVRAM in the RTC address-space portion of the RTC chip. Tests the following registers: NVR_SEC NVR_SECALRM NVR_MI NVR_MINALRM NVR_HOUR NVR_HOURALRM NVR_WEEKDAY NVR_DAY NVR_MONTH NVR_YEAR NVRAM tested is in the range 0xE – 0x3F.
epc_rtcinc	RTC increment test	Tests the ability of the RTC chip to handle time-of-day transitions. Sets the RTC to a known time and date (last second of the year), waits one second, then checks to make sure that the time and date have changed correctly.
epc_rtcint	RTC interrupt generation test	Tests to make certain the RTC can correctly generate Alarm, Periodic, and Update interrupts. Validates the path from the RTC chip to the IP board's master CPU.
duart_loopback	Dual Asynchronous Receiver/Transmitter (DUART) loopback test.	Attempts to configure and test all available serial ports. Performs loopback testing at all baud rates for each port tested. Normally, the test uses the internal loopback, but if you run it with the `-e` option, the test assumes an external loopback fixture is being used.

IP19 IDE Tests

The IP19 IDE tests are divided into four categories:

IP tests, described in Section 6.4.1, "IP Tests"
Translation lookaside buffer (TLB) tests, described in Section 6.4.2, "Translation Lookaside Buffer (TLB) Tests"
Floating-point unit (FPU) tests, described in Section 6.4.3, "Floating-Point Unit (FPU) Tests"
Cache tests, described in Section 6.4.4, "Cache Tests"

To start an IP19 IDE test, boot IDE from the Command Monitor. See Section 6.2, "Running an IDE Test."

Set the desired report level. The default report level is 2.

Available report levels are shown in Table 6-6.

Table 6-6. IP19 IDE Report Levels

Report Level	Function	Comments
Level 5	Displays debugging messages.	Too much detail for most testing scenarios.
Level 4	Prints out memory locations as they are written.	Increases testing time.
Level 3	Prints out one-line functional descriptions within tests.	Probably the most useful level for general testing.
Level 2 (default)	Prints out only errors and titles.	This is the default level.
Level 1	Prints out only titles and pass/fail

Each test level prints out messages for that level and all lower levels.

There are several commands that run a battery of tests. These commands are:

`ipall`		Invokes tests `ip1` through `ip8`.
`tlball`		Invokes tests `tlb1` through `tlb9`
`fpuall`		Invokes tests `fpu1` through `fpu14`.
`cacheall`		Invokes tests `cache1` through `cache48`.
`ip19`		Invokes all IP, TLB, FPU and CACHE tests.
`cache49`		Invokes a short version of `cache48`.
`cstate`[0 - 21]		Invokes individual cache state tests in `cache48`.
`quickfpu`		Invokes tests `fpu1` through `fpu13`, skipping `fpu14`.
`quickcache`		Invokes tests `cache1` through `cache44`, then `cache47`, skipping `cache45`, `cache46` and `cache48`.
`quickip19`		Invokes all IP, TLB, FPU and CACHE tests except `fpu14`, `cache45`, `cache46` and `cache48`.
`ipresults`		Displays the test summaries for `ipall`.
`tlbresults`		Displays the test summaries for `tlball`.
`fpuresults`		Displays the test summaries for `fpuall` or `quickfpu`.
`cacheresults`		Displays the test summaries for `cacheall` or `quickcache`.
`ip19results`		Displays the test summaries for `ip19` or `quickip19`. This command is automatically invoked at the end of `ip19` and `quickip19`.

Identifying IP19 IDE Test Messages

All IP19 IDE error messages are preceded by a number that identifies the message and helps isolate the problem. The syntax for the numbers is:

01ccnnn

The numbers are interpreted as follows:

01 - the board id for IP19
cc - a hint for failed component(s):
01 - A chip
02 - D chip
03 - CC chip
04 - Primary cache
05 - Secondary cache
06 - R4400
07 - Primary or secondary cache
08 - TLB
09 - FRU
nnn - the error id

IP Tests

There are eight IP tests. These test components that are not covered by the TLB, FPU, and CACHE tests. Table 6-7 summarizes the IP test commands:

Table 6-7. IP19 IP Test Summary

Test	Function	Description
ip1 (local_regtest)	Checks cache-coherency (CC) local registers	Performs read/write tests on some CC registers and read tests on some read-only registers.
`ip2 (cfig_regtest)`	Checks configuration registers	Performs read/write tests of the configuration registers.
ip3 (bustags_reg)	Checks bus tags	Calculates the size of bus tags based on the size of the secondary cache. Then it performs a read/write test on the bus tags.
ip4 (counter)	Checks R4000/R4400 count/compare registers	Performs a basic write/read test on the R4000/R4400 compare register. Then it generates an interrupt using the R4000/R4400 count and compare registers.
ip5 (intr_level0)	Checks IP19 level 0 interrupt	Generates level 0 interrupts at different priority values and execution levels. It also checks multiple level 0 interrupts occurring at the same time.
ip6 (intr_level3)	Checks IP19 level 3 interrupt	This test generates level 3 interrupts using the EV_ERTOIP register.
ip7 (intr_timer)	Checks IP19 RTSC and interval timer	Generates level 1 interrupts by writing a value into the EV_CMPREG configuration registers so that the RTSC will reach this value and interrupts the processor.
ip8 (intr_group)	Checks IP19 processor group interrupt	This test generated level 0 interrupts using different processor groups at different priority levels including broadcast interrupts.

The following sections provide details about each test.

ip1 (local_regtest) - Check CC Local Registers

Basic write/read test for the local registers. The registers tested are limited to the following:

EV_WGDST		Write gatherer destination
EV_WGCNTRL		Write gatherer control
EV_IPO		Interrupts 63 - 0
EV_IP1		Interrupts 127 - 64
EV_CEL		Current execution level
EV_IGRMASK		Interrupt group mask
EV_ILE		Interrupt level enable
EV_ERTOIP		Error/timeout interrupt
EV_ECCSB_DIS		ECC single-bit error disable

The read-only registers are read and their contents are reported. These registers are:

EV_SPNUM		Slot/Processor info
EV_SYSCONFIG		System configuration
EV_HPIL		Highest pending interrupt level
EV_RO_COMPARE		RTC compare
EV_RTC		Real time clock
EV_WGCOUNT		Write gatherer count

Possible errors:

0103001: Local register n R/W error: Wrote value1 Read value2

In the above error message, n is the register name, value1 is the value written and value2 is the value read.

ip2 (cfig_regtest) - Check Configuration Registers

Basic write/read test for the configuration registers. The registers tested are limited to the following:

EV_PGBRDEN		Write gatherer destination
EV_PROC_DATARATE		Write gatherer control
EV_WGRETRY_TOUT		Interrupts 0 - 63
EV_CACHE_SZ		Interrupts 64 - 127
EV_CMPREGO - 3		Timer comparator registers

Note: The timer comparator registers are checked via the read-only RTC compare register.

Possible error:

0103002: Configuration Register %s R/W error : Wrote 0x%llx Read 0x%llx

ip3 (bustags_reg) - Check Bus Tags

This test calculates the size of bus tag space based on the size of the secondary cache. Then it performs basic write/read test on the bus tags.

Possible error:

0103003: Bus tag addr 0x%x R/W error : Wrote 0x%x Read 0x%x

ip4 (counter) - Check R4K Count/compare Test

This test performs a basic write/read test on the R4K compare register first. Then it generates an interrupt using the R4K count and compare registers.

Possible errors:

0106001: Compare register data error : Expected 0x%x Got 0x%x
0106002: Incorrect contents in count register : Expected 0x%x Got 0x%x
0106003: Phantom count/compare interrupt received
0106004: No count/compare interrupt received : Count 0x%x Compare 0x%x

ip5 (intr_level0) - Check IP19 Level 0 Interrupt

This test generates level-0 interrupts at different priority values and execution levels. It also checks multiple level-0 interrupts occurring at the same time.

Possible errors:

0103004: Level 0 interrupt pending failure : Priority 0x%x IP0 0x%llx IP1 0x%llx
0103005: Level 0 highest priority interrupt level failure : HPIL 0x%llx
0103006: Level 0 interrupt not indicated in Cause register 0x%x
0103007: Level 0 interrupt pending not cleared : IP0 0x%llx IP1 0x%llx
0103002: Configuration register %s R/W error : Wrote 0x%llx Read 0x%llx
0103008: Level 0 highest priority interrupt level not cleared : HPIL 0x%llx
0103009: Level 0 interrupt pending not cleared in Cause register : Cause 0x%x
010300a: Level 0 current exec level mismatch : Wrote 0x%llx Read 0x%llx
010300b: Level 0 interrupt not detected when priority >= CEL : Cause 0x%
010300c: Level 0 interrupt detected when priority < CEL : Cause 0x%x
010300d: Level 0 interrupt pending not cleared : Cause 0x%x
010300e: Level 0 highest priority interrupt level incorrect : Expected 0x7f Got 0x%llx
010300f: Level 0 multiple interrupt pending incorrectly indicated : Expected 0x6000000000000009 Got 0x%llx
0103010: Level 0 multiple interrupt pending incorrectly indicated : Expected 0x9000000000000006 Got 0x%llx
0103011: Level 0 multiple interrupt pending not cleared : IP0 0x%llx
0103012: Level 0 multiple interrupt pending not cleared : IP1 0x%llx
0103013: Level 0 multiple interrupt HPIL not cleared : HPIL 0x%llx
0103014: Level 0 multiple interrupt Cause not cleared : Cause 0x%x
0103015: Level 0 interrupt did not occur : Priority 0x%x

ip6 (intr_level3) - Check IP19 Level 3 Interrupt

This test generates level-3 interrupts using the EV_ERTOIP register.

Possible errors:

0103016: Level 3 interrupt pending not detected in CAUSE
0103017: Interrupting error not detected in ERTOIP
0103018: Level 3 interrupt pending not cleared in Cause : Cause 0x%x
0103019: ERTOIP not cleared via write to CERTOIP : ERTOIP 0xllx
010301a: Level 3 interrupt did not occur : ERTOIP 0x%llx

ip7 (intr_timer) - Check IP19 RTSC and Interval Timer

This test generates level-1 interrupt by writing a value into the EV_CMPREG configuration registers so that the RTSC will reach this value and interrupts the processor.

Possible errors:

010301b: Invalid timer interrupt occurred
010301c: Interval timer interrupt did not occur
010301d: Group interrupt pending not cleared in Cause : Cause 0x%x

ip8 (intr_group) - Check IP19 Processor Group Interrupt

This test generated level 0 interrupts using different processor groups at different priority levels including broadcast interrupts.

Possible errors:

010301e: Group interrupt pending not set correctly in EV_IP0 : Expected 0x%llx Got 0x%llx
010301f: Group highest priority interrupt level failure : HPIL 0x%llx
0103020: Group interrupt not indicated in Cause register 0x%x
0103021: Group interrupt pending not cleared : IP0 0x%llx IP1 0x%llx
0103022: Group highest priority interrupt level not cleared : HPIL 0x%llx
0103023: Group interrupt pending not cleared in Cause register : Cause 0x%x
0103024: Group interrupt did not occur : group 0x%x priority 0x%x
0103025: Group interrupt pending not cleared in Cause : Cause 0x%x

Translation Lookaside Buffer (TLB) Tests

There are nine TLB tests that check the translation lookaside buffer in the MIPS R4000/R4400. They are described in the following sections.

tlb1 (tlb_ram) - Test R4K TLB as RAM

Tests the TLB as a small memory array. Checks to see that all read/write bits can be toggled and that all undefined bits read back zero.

Possible errors:

0108001: TLBHI      entry %d R/W error: Wrote 0x%x Read 0x%x
0108002: TLBLO even entry %d R/W error: Wrote 0x%x Read 0x%x
0108003: TLBLO odd  entry %d R/W error: Wrote 0x%x Read 0x%x

tlb2 (tlb_probe) - Check TLB Functionality

Sets up all the TLB slots and then probes them with matching addresses. Checks to ensure that there is a response for each valid address.

Possible error:

0108018: TLB probe error : Expected entry %d Got entry %d vpnum %d addr 0x%x

tlb3 (tlb_xlate) - Check TLB Address Translation

Tests for correct virtual to physical translation via mapped TLB entries. Sets the virtual address to user segment and uncached.

Possible errors:

010801b: TLB entry %d unexpected exception for addr 0x%x
010801c: TLB entry %d translation error at addr 0x%x : Wrote %d Read %d

tlb4 (tlb_valid) - Check TLB Valid Exception

Tests to see if TLB invalid accesses generate exceptions. Maps the TLB entries to invalid addresses in k2seg and attempts to access them.

Possible errors:

0108016: TLB entry %d invalid exception VADDR error : Expected 0x%x Got 0x%x
0108017: TLB entry %d invalid exception didn't occur

tlb5 (tlb_mod) - Check TLB Modification Exception

This test sets up the TLB to map each page as nonwritable, then attempts to write to each of the mapped pages. It verifies that an exception is generated for each write attempt.

Possible errors:

010800b: TLB %s entry %d mod exception VADDR error : Expected 0x%x Got 0x%x
010800c: TLB %s entry %d mod exception didn't occur
010800d: TLB %s entry %d unexpected exception during mod
010800e: TLB %s entry %d mod error : Wrote 0x%x Read 0x%x

tlb6 (tlb_pid) - Check TLB Refill Exception

Tests each TLB slot by attempting access with both matching and nonmatching process id. It verifies that matching PID accesses are allowed and nonmatching PID accesses generate exceptions.

Possible errors:

0108015: TLB %s entry %d unexpected exception with matching pid 0x%x
0108016: TLB %s entry %d refill exception VADDR error : Expected 0x%x Got 0x%x
0108017: TLB %s entry %d refill exception didn't occur

tlb7 (tlb_g) - Check Global Bit In TLB Entry

Sets up all the TLB slots to allow global access, then attempts access on all slots with a variety of different PID settings. This test passes only if no invalid access exceptions occur.

Possible error:

010801d: Unexpected exception occurred during global access

tlb8 (tlb_c) - Check C Bits In TLB Entry

Attempts to access TLB-mapped memory in both cached and uncached modes. Tests all slots by writing and reading back a pattern, first in cached mode, then in uncached mode. This test checks basic functionality, and does not attempt to detect cached/uncached interactions.

Possible errors:

010800f: Exception during cached write to 0x%x
0108010: Cached write to 0x%x failed
0108011: TLB %s entry %d cached mode exception
0108012: TLB %s entry %d cached R/W error : Wrote 0x%x Read 0x%x
0108013: TLB %s entry %d uncached mode exception
0108014: TLB %s entry %d uncached R/W error : Wrote 0x%x Read 0x%x

tlb9 (tlb_mapuc) - Check Cached/Uncached TLB Access

Checks that both cached and uncached mapped accesses work without interfering with each other. The purpose of this test is to detect the R4000/R4400 mapped uncached writeback bug. To do this, the test sets up two TLB entries for the same page of physical memory, one using cached access and the other using uncached entries. A write is done via each of the TLB entries, followed by a read. If the R4000/R4400 cache is working properly, the test will be able to read back the correct (different) pattern for each access mode, because the code avoids flushing the cache to main memory. If the bug is present, the same value will be read back via both cached and uncached access. The writes are done in both cached/uncached and uncached/cached orders.

Possible errors:

0108004: TLB %s entry %d cached/uncached W exception
0108005: TLB %s entry %d cached/uncached W error : Wrote 0x%x Read 0x%x
0108006: TLB %s entry %d uncached/cached W execption
0108007: TLB %s entry %d uncached/cached W error : Wrote 0x%x Read 0x%x

Floating-Point Unit (FPU) Tests

There are fourteen floating-point unit tests that check the FPU in the MIPS R4000/R4400. These are described in the following sections.

fpu1 (fpregs) - FPU Register Test

This test simply writes and reads the FPU registers, reporting any readback errors.

Possible errors:

010901e: FP register %d data error : Expected 0x%x Got 0x%x
010901f: FP register %d inverted data error : Expected 0x%x Got 0x%x

fpu2 (fpmem) - FPU Load/Store Memory Test

Loads FPU from memory and stores memory from FPU.

Possible errors:

010901c: Load/store FP reg %d data error : Expected 0x%x Got 0x%x
010901d: Load/store FP reg %d inverted data error : Expected 0x%x, Got 0x%x

fpu3 (faddsubs) - FPU Add/Subtract (Single Precision)

Tests addition and subtraction using simple single-precision arithmetic.

Possible errors:

0109004: FP single add/sub result error : Expected 0x%x Got 0x%x
0109005: FP single add/sub status error : Expected 0 Got 0x%x
0109006: Fixed to single conversion failed : Before 0x%x After 0x%x

fpu4 (faddsubd) - FPU Add/Subtract (Double Precision)

Tests addition and subtraction using simple double-precision arithmetic.

Possible errors:

0109001: FP double add/sub result error : Expected 0x%x Got 0x%x
0109002: FP double add/sub status error : Expected 0 Got 0x%x
0109003: Fixed to double conversion failed : Before 0x%x After 0x%x

fpu5 (fmuldivs) - FPU Multiply/Divide (Single Precision)

Tests multiplication and division using simple single-precision arithmetic.

Possible errors:

0109011: FP single divide result error : Expected 0x%x Got 0x%x
0109012: FP single multiply result error : Expected 0x%x Got 0x%x

fpu6 (fmuldivd) - FPU Multiply/Divide (Double Precision)

Tests multiplication and division using simple double-precision arithmetic.

Possible errors:

010900f: FP double divide result error : Expected 0x%x Got 0x%x
0109010: FP double multiply result error : Expected 0x%x Got 0x%x

fpu7 (fmulsubs) - FPU Multiply/Subtract (Single Precision)

Tests multiplication and subtraction using simple single-precision arithmetic.

Possible errors:

0109016: FP single mul/div result error : Expected 0x%x Got 0x%x
0109017: Fixed to single conversion failed : Before 0x%x After 0x%x
0109018: FP single mul/div status error : 0x%x

fpu8 (fmulsubd) - FPU Multiply/Subtract (Double Precision)

Tests multiplication and subtraction using simple double-precision arithmetic.

Possible errors:

0109013: FP double mul/sub result error : Expected 0x%x Got 0x%x
0109014: Fixed to double conversion failed : Before 0x%x After 0x%x
0109015: FP double mul/div status error : 0x%x

fpu9 (finvalid) - FPU Invalid Test

Simple test to see if an invalid operation exception can be generated. Divides 0.0 by itself to generate the exception.

Possible errors:

010900b: Invalid exception didn't occur
010900c: Invalid exception status error : 0x%x
010900d: Invalid exception dividend error : Expected 0x%x Got 0x%x

fpu10 (fdivzero) - FPU Divided by Zero Test

Divides a non-zero value by 0.0. Unlike the previous test, the floating-point status register is checked after the exception to make sure the divide-by-zero flag is set.

Possible errors:

0109007: Divide by Zero exception status error : 0x%x
0109008: Dividend conversion failed : Before 0x%x After 0x%x
0109009: Divisor conversion failed : Before 0x%x After 0x%x

fpu11 (foverflow) - FPU Overflow Test

Generates a single-precision overflow by adding 2 at-the-limit large values. After the exception, the floating-point status register is checked to make sure the overflow flag was set.

Possible error:

0109019: Overflow exception status error : 0x%x

fpu12 (funderflow) - FPU Underflow Test

Generates a single-precision overflow by dividing an at-the-limit small value by 2. After the exception, the floating-point status register is checked to make sure the underflow flag was set.

Possible errors:

0109020: Exception other than Underflow in FCR31 : 0x%x
0109021: Failed to generate Underflow Exception

fpu13 (finexact) - FPU Inexact Test

Generates a single-precision inexact conversion error by attempting to convert an integer value too large for a single-precision representation into a single precision value. After the error, the floating-point status register is checked to make sure the inexact conversion flag was set.

Possible error:

010900a: Inexact exception status error : 0x%x

fpu14 (fpcmput) - FPU Computation Test

Given a list of infinite series, this test executes them a specified number of times and compares the result gotten at run-time with an expected result. Discrepancies are reported. This is a slow test.

Possible errors:

010900e: FP computation unexpected exception : 0x%x
010901a: Single precision %s error : Expected 0x%x Got 0x%x
010901b: Double precision %s error : Expected 0x%x 0x%x Got 0x%x 0x%x

Cache Tests

There are forty-eight tests to check the primary and secondary cache of the MIPS R4000/R4400. They are described in the following sections.

cache1 (Taghitst) - TagHi Register Test

This tests the data integrity of the TagHi register. A sliding-one and a sliding-zero pattern are used.

Possible errors:

0104001: Taghi register failed walking one test
         Expected data: 0x%08x Actual data: 0x%08x
0104002: Taghi register failed walking zero test
         Expected data: 0x%08x Actual data: 0x%08x

cache2 (Taglotst) - TagLo Register Test

This tests the data integrity of the TagLo register. A sliding-one and a sliding-zero pattern are used.

Possible errors:

0104003: Taglo register failed walking one test
         Expected data: 0x%08x Actual data: 0x%08x
0104004: Taglo register failed walking zero test
         Expected data: 0x%08x Actual data: 0x%08x

cache3 (pdtagwlk) - Primary Data TAG RAM Data Line Test

This checks the data integrity of the primary data TAG RAM path using walking-ones and walking-zeros patterns.

Possible error:

0104005: D-cache tag ram data line error
         Failed walking one (or zero) test at 0x%08x
         Expected: 0x%08x Actual 0x%08x

cache4 (pdtagadr) - Primary Data TAG RAM Address Line Test

This tests the address lines to the primary data cache TAG RAM by sliding a one and then a zero on the address lines. This test assumes that the TagLo register is in good working condition, and therefore you should run the cache2 (Taglotst) test before this one.

Possible error:

0104006: D-cache tag ram address line error
         Failed walking one (or zero) test at 0x%08x
         Expected: 0x%08x Actual 0x%08x

cache5 (PdTagKh) - Primary Data TAG Knaizuk Hartmann Test

This tests the data integrity of the primary data cache TAG RAM with the Knaizuk Hartmann algorithm. It treats the TAG RAM array as a ordinary memory array. The parity bit is not checked in this test.

Note: This algorithm is used to perform a fast but nonexhaustive memory test. It will test a memory subsystem for stuck-at faults in both the address lines as well as the data locations.

The algorithm breaks up the memory to be tested into 3 partitions. Partition 0 consists of memory locations 0, 3, 6, ...; partition 1 consists of memory locations 1,4,7,...; partition 2 consists of locations 2,5,8...; The partitions are filled with either an all-ones pattern or an all-zeros pattern. By varying the order in which the partitions are filled and then checked, this algorithm checks all combinations of possible stuck-at-faults.

Possible errors:

0104007: Partition 1 error after partition 0 set to 0xaaaaaaaa
0104008: Partition 2 error after partition 1 set to 0xaaaaaaaa
0104009: Partition 0 error after partition 1 set to 0xaaaaaaaa
010400a: Partition 1 error after partition 1 set to 0xaaaaaaaa
010400b: Partition 0 error after partition 0 set to 0x55555555
010400c: Partition 2 error after partition 2 set to 0xaaaaaaaa

For each of the above errors, the following additional information is also provided:

Tag ram address: 0x%08x
Expected: 0x%08x Actual: 0x%08x Xor: 0x%08x

cache6 (pitagwlk) - Primary Instruction TAG RAM Data Line Test

This checks the data integrity of the primary instruction cache TAG RAM path using a walking ones and zeros pattern.

Possible error:

010400d: I-cache tag ram data line error
         Failed sliding one (or zero) test at 0x%08x
         Expected: 0x%08x, Actual: 0x%08x

cache7 (pitagadr) - Primary Instruction TAG RAM Address Line Test

This tests the address lines to the primary instruction cache TAG RAM by sliding a one and then a zero on the address lines. This test assumes that the TagLo register is in good working condition.

Possible error:

010400e: I-cache tag ram address line error
         Failed sliding one (or zero) test at 0x%08x
         Expected: 0x%08x Actual 0x%08x

cache8 (PiTagKh) - Primary Instruction TAG RAM Knaizuk Hartmann Test

This tests the data integrity of the primary instruction cache TAG RAM with the Knaizuk Hartmann algorithm. It treats the TAG RAM array as a ordinary memory array. The parity bit is not checked in this test.

Possible errors:

010400f: Partition 1 error after partition 0 set to 0xaaaaaaaa
0104010: Partition 2 error after partition 1 set to 0xaaaaaaaa
0104011: Partition 0 error after partition 1 set to 0xaaaaaaaa
0104012: Partition 1 error after partition 1 set to 0xaaaaaaaa
0104013: Partition 0 error after partition 0 set to 0x55555555
0104014: Partition 2 error after partition 2 set to 0xaaaaaaaa

For each of the above errors, the following additional information is provided:

Tag ram index address: 0x%08x
Expected: 0x%08x Actual: 0x%08x Xor: 0x%08x

cache9 (sd_tagwlk) - Secondary TAG Data Path Test

This checks the data integrity of the secondary data TAG RAM path using a walking-ones or walking-zeros pattern.

Possible error:

0105015: Secondary Data TAG RAM Path Error
         on sliding one (or zero) pattern
         TAG RAM Location 0x%x
         Expected 0x%x  Actual= 0x%x  XOR= 0x%x

cache10 (sd_tagaddr) - Secondary TAG Address Test

This checks the address integrity to the primary data TAG RAM by using a walking address.

Possible error:

0105016: Secondary Data TAG Address Error
         TAG RAM Location 0x%x
         Expected 0x%x  Actual= 0x%x  XOR= 0x%x

cache11 (sd_tagkh) - Secondary TAG RAM Knaizuk Hartmann Test

This tests the data integrity of the secondary data cache TAG RAM with the Knaizuk Hartmann algorithm. It treats the TAG RAM array as a ordinary memory array. The parity bit is not checked in this test.

Possible error:

0105017: Secondary Data TAG ram data Error
         Address %x, error code %d
         expected %x, actual %x, XOR %x

cache12 (d_tagparity) - Primary Data TAG RAM Parity Test

This tests the functionality of the parity bit in the primary data cache tag. For each tag, a stream of ones and zeros are shifted into the tag to check if the parity bit change state accordingly.

Possible error:

0104018: D-cache tag ram parity bit error
         Tag ram address: 0x%08x expected content: 0x%08x
         Taglo: 0x%08x expected parity: 0x%x actual parity: 0x%x

cache13 (d_tagcmp) - Primary Data TAG Comparator Test

This tests the comparator at the D-cache tag for hit and miss detection. For each tag, it sets the ptag field with the values that will cause a cache hit for the Kseg0 address of 0x80002000 to 0x9fffffff. The values used are a walking-one or a walking-zero pattern. This ensure only one bit location is tested at the comparator. The cache operation Hit Invalidate is used to check for cache hit and miss situations.

Possible errors:

0104019: D-cache tag comparator did not detect a miss
0104020: D-cache tag comparator did not detect a hit

For each of the above errors, the following additional information is provided:

Tag ram address: 0x%08x
PTag field of tag: 0x%06x comparing with PFN: 0x%06x

cache14 (d_tagfunct) - Primary Data TAG Functionality Test

This tests the functionality of the data cache tag. Kseg0 addresses are used to load the cache from memory. The ptag and the cache state field are checked to see if they are holding expected values. Virtual addresses 0x80000000, 0x80002000, 0x80004000, 0x80008000, ... 0x90000000 are used as the base address of an 8k page which is mapped to the cache. The ptag and state of each cache line are checked against the expected value.

cache15 (d_slide_data) - Primary Data RAM Data Line Test

Possible errors:

0104021: D-cache tag functional error in PTAG field
         PTag field does not contain correct tag bits
         Cache line address: 0x%08x
         Expected PTag: 0x%06x
         Actual PTag: 0x%06x
         TAGLO Register %x
         Re-read DTAG %x
0104022: D-cache tag functional cache state error
         Cache line address: 0x%08x
         Expected cache state: 0x%08x
         Actual cache state: 0x%08x
         TAGLO Register %x
         Re-read DTAG %x

cache15 (d_slide_data) - Primary Data RAM Data Line Test

This tests the data lines to the primary data cache. A sliding one and a sliding zero data pattern is written into the first location of the D-cache to check if each data line can be toggled individually.

Possible errors:

0107023: D-cache data ram data lines failed walking one test
         Addr: 0x%08x Expected: 0x%08x Actual: 0x%08x Xor: 0x%08x
0107024: D-cache data ram data lines failed walking zero test
         Addr: 0x%08x Expected: 0x%08x Actual: 0x%08x Xor: 0x%08x

cache16 (d_slide_addr) - Primary Data RAM Address Line Test

This tests the address lines to the primary data cache. Each address line to the data cache is toggled once individually by sliding a one and then a zero across the address lines.

Possible errors:

0107025: D-cache data ram address lines failed walking one test
         Addr: 0x%08x Expected: 0x%08x Actual: 0x%08x Xor: 0x%08x
0107026: D-cache data ram address lines failed walking zero test
         Addr: 0x%08x Expected: 0x%08x Actual: 0x%08x Xor: 0x%08x

cache17 (d_kh) - Primary Data RAM Knaizuk Hartmann Test

This tests the data integrity of the D-cache with the Knaizuk Hartmann algorithm. Data pattern 0x55555555 and 0xaaaaaaaa are used.

Possible errors:

0107027: Partition 1 error after partition 0 set to 0xaaaaaaaa
0107028: Partition 2 error after partition 1 set to 0xaaaaaaaa
0107029: Partition 0 error after partition 1 set to 0xaaaaaaaa
010702a: Partition 1 error after partition 1 set to 0xaaaaaaaa
010702b: Partition 0 error after partition 0 set to 0x55555555
010702c: Partition 2 error after partition 2 set to 0xaaaaaaaa
For each of the above errors, the following additional information is provided:
         Cache address: 0x%08x
         Expected: 0x%08x Actual: 0x%08x Xor: 0x%08x

cache18 (dsd_wlk) - Primary/Secondary Data Path Test

Tests the data path from memory through the secondary cache and to the primary data cache.

Possible errors:

010702d: Data Path Error from Memory->Secondary->Primary Data
         Address %x, expected %x, actual %x, Xor %x
010702e: Data Path Error from Primary ->Secondary->Memory Data
         Address %x, Expected %x, Actual %x, Xor %x

cache19 (sd_aina) - Secondary Data RAM (Address in Address) Test

Performs an "address in address" test on the secondary data cache.

Possible errors:

010502f: Secondary Memory Error on pattern 1
         Address %08x
         expected %08x, actual %08x, XOR %08x
0105030: Secondary Memory Error on pattern 2
         Address %08x
         expected %08x, actual %08x, XOR %08x

cache20 (d_function) - Primary Data Functionality Test

This tests the functionality of the entire data cache. It checks the block fill, write back on a dirty line replacement, and no write back on a clean line replacement function of the data cache lines.

Possible errors:

0104031: D-cache block fill error 1
         Cache contains incorrect data
         Cache Address: 0x%08x
         Expected: 0x%08x Actual: 0x%08x Xor: 0x%08x
0104032: D-cache block fill error 2
         Cache contains incorrect data
         Cache Address: 0x%08x
         Expected: 0x%08x Actual: 0x%08x Xor: 0x%08x
0104033: D-cache block write back error 1
         Memory contains incorrect data
         Cache Address: 0x%08x
         Expected: 0x%08x Actual: 0x%08x Xor: 0x%08x
0104034: D-cache block fill error 3
         Cache contains incorrect data
         Cache Address: 0x%08x
         Expected: 0x%08x Actual: 0x%08x Xor: 0x%08x
0104035: D-cache block write back error 2
         Memory content is altered
         Write back happened on a clean line
         Cache Address: 0x%08x
         Expected: 0x%08x Actual: 0x%08x Xor: 0x%08x

cache21 (d_parity) - Primary Data Parity Generation Test

This tests the parity bit generation of the D-cache data RAM.

Possible error:

0104036: D-cache parity generation error
         error %x
         Cache byte address: 0x%08x data:0x%02x
         Parity bit position: 0x%02x
         Expected parity: 0x%02x Actual parity:0x%02x

cache22 (i_tagparity) - Primary Instruction TAG RAM Parity Bit Test

This tests the functionality of the parity bit in the primary I-cache tag. For each tag, the parity bit is tested to respond to each bit change in the tag.

Possible error:

0104037: I-cache tag ram parity bit error
         Tag ram address: 0x%08x expected content: 0x%08x
         Taglo: 0x%08x expected parity: 0x%x actual parity: 0x%x

cache23 (i_tagcmp) - Primary Instruction TAG RAM Comparitor Test

This tests the comparator at the I-cache tag for hit and miss detection.

Possible errors:

0104038: I-cache tag comparator did not detect a miss (walking l)
0104039: I-cache tag comparator did not detect a hit (walking 1)
010403a: I-cache tag comparator did not detect a miss (walking zero)
010403d: I-cache tag comparator did not detect a hit (walking zero)

For each of the above errors, the following additional information is provided:

Tag ram address: 0x%08x
PTag field of tag: 0x%06x comparing with PFN: 0x%06x

cache24 (i_tagfunct) - Primary Instruction TAG Functionality Test

This tests the functionality of the instruction cache tag. Kseg0 addresses are used to load the cache from memory. This will test if the cache is functional on the cachable memory space. After each 8k segment of memory is loaded into the cache, the ptag and the cache state field are checked to see if they are holding expected values. Virtual addresses 0x80000000, 0x80002000, 0x80004000, 0x80008000, ..., 0x90000000 are used as the base address of each 8k page that is mapped to the cache. The ptag and cache state of each cache line are checked against the expected value.

Possible errors:

010403b: I-cache tag functional error in PTAG field
         PTag field does not contain correct tag bits
         Cache line address: 0x%08x
         Expected PTag: 0x%06x
         Actual PTag: 0x%06x
010403c: I-cache tag functional cache state error
         Cache state not correct
         Cache line address: 0x%08x
         Expected cache state: 0x%08x
         Actual cache state: 0x%08x

cache25 (i_slide_data) - Primary Instruction Data RAM Data Line Test

This checks the data lines to the I-cache data RAM by sliding a one and zero bit across the bus.

Possible errors:

010403f: I-cache data ram data lines failed walking one test
         Addr: 0x%08x Expected: 0x%08x Actual: 0x%08x Xor: 0x%08x
         PITAG  %x
         PDTAG  %x
         STAG  %
0104040: I-cache data ram data lines failed walking zero test
Addr: 0x%08x Expected: 0x%08x Actual: 0x%08x Xor: 0x%08x
         PTAG  %x
         STAG  %x

cache26 (i_aina) - Primary Instruction Data RAM Address In Address Test

Performs an address in address test on the primary instruction cache.

Possible error:

0107041: I-cache address in address error
         addr %x, exp %x, act %x, XOR %x

cache27 (i_function) - Primary Instruction Functionality Test

This tests the functionality of the entire instruction cache. It checks the block fill and hit write back of the instruction cache lines.

Possible error:

0107042: I-cache block write back error
Memory contains incorrect data
Cache address: 0x%08x
Expected: 0x%08x Actual: 0x%08x Xor: 0x%08x
Icache TAG = %x
Scache TAG = %x

cache28 (i_parity) - Primary Instruction Parity Generation Test

This tests the parity bit generation of the I-cache data RAM.

Possible error:

0104043: I-cache parity generation error
error %x
Cache byte address: 0x%08x data:0x%02x
Parity bit position: 0x%02
Expected parity: 0x%02x Actual parity:0x%02x

cache29 (i_hitinv) - Primary Instruction Hit Invalidate Test

This tests the Hit Invalidate cache operation on the instruction cache.

Possible errors:

0104044: I-cache state error during initialization
Cache state did not change to valid when filled from memory
Cache line address: 0x%08x
Expected cache state: 0x%08x Actual cache state: 0x%08x
0104045: I-cache state error
Hit Invalidate changed the line to invalid on a miss
Cache line address: 0x%08x
Miss address: 0x%08x
Expected cache state: 0x%08x Actual cache state: 0x%08x
0104046: I-cache state error on a Hit Invalidate Cache OP
Hit Invalidate did not invalidate the line on a hit
Cache line address: 0x%08x
Expected cache state: 0x%08x Actual cache state: 0x%08x

cache30 (i_hitwb) - Primary Instruction Hit Writeback Test

This tests the Hit Writeback cache operation on the instruction cache.

Possible errors:

0104047: I-cache state error during initialization
Cache state did not change to valid when filled from memory
Cache line address: 0x%08x
Expected cache state: 0x%08x Actual cache state: 0x%08x
0104048: I-cache state error Hit writeback happened on a cache miss
Cache line address: 0x%08x
Miss address: 0x%08x
0104049: I-cache Hit writeback did not happen on a cache hit
Cache line address: 0x%08x
expected %x, actual %x, XOR %x

cache31 (ECC_reg_tst) - ECC Register Test

This tests the data integrity of the ECC register. Sliding one and sliding zero patterns are used in this test.

Possible errors:

010404a: ECC register failed walking one test
Expected data: 0x%08x Actual data: 0x%08x
010404b: ECC register failed walking zero test
Expected data: 0x%08x Actual data: 0x%08x

cache32 (dd_hitinv) - Primary Data Hit Invalidate Test

This tests the Hit Invalidate cache operation on the data cache.

Possible errors:

010404c: D-cache state error during initialization
Cache state did not change to valid when filled from memory
Cache line address: 0x%08x
Expected cache state: 0x%08x Actual cache state: 0x%08x
010404d: D-cache state error
Hit Invalidate changed the line to invalid on a miss
Cache line address: 0x%08x
Miss address: 0x%08x
Expected cache state: 0x%08x Actual cache state: 0x%08x
010404e: D-cache state error on a  Hit Invalidate Cache OP
Hit Invalidate did not invalidate the line on a hit
Cache line address: 0x%08x
Expected cache state: 0x%08x Actual cache state: 0x%08x

cache33 (d_hitwb) - Primary Data Hit Writeback Test

This is hit writeback cache operation on the data cache.

Possible errors:

010404f: D-cache state error during initialization
Cache state did not change to valid when filled from memory
Cache line address: 0x%08x
Expected cache state: 0x%08x Actual cache state: 0x%08x
TAGLO Reg %x
Re-Read dtag %x
Re-Read stag %x
0104050: D-cache state error Hit writeback happened on a clean exclusive line
Cache line address: 0x%08x
PTAG %x
Scache TAG %x
0104051: D-cache Hit writeback happened on a cache miss
Cache line address: 0x%08x
Miss address: 0x%08x
PTAG %x
Scache TAG %x
0104052: D-cache Hit writeback did not happen on a cache hit
Cache line address: 0x%08x
PTAG %x
Scache TAG %x
0104053: D-cache Hit Writeback clears the write back bi
Cache line address: 0x%08x

cache34 (d_dirtywbw) - Primary Data Dirty Writeback Word Test

This verifies the block (four words) write mode in data cache. It writes to K0 (0x80020000) cached space, causing the cache to be marked dirty. Then it replace the cache line by reading 0x80022000, a different cache line with same offset. This causes the data in 0x80020000 to writeback to memory, which now has the same data as in 0x80020000. Multiple cache lines are tested back to back.

Possible errors:

0104054: Unexpected Cache write through to memory
addr %x, expected %x, actual %x, XOR %x
Seconday TAG %x
0104055: Cache writeback did not occur on a word store to a dirty line
addr %x
expected %x, actual %x, XOR %x
Seconday TAG %x

cache35 (d_refill) - Primary Data Refill from Secondary Cache Test

This verifies the block write/read mode in data cache. It writes to K0 (0x80020000) cached space, causing the cache to become dirty. Then it replaces the cache line by reading 0x80022000, which is a different cache line with same offset. This causes the data in primary data cache to be written back to the secondary. The address 0x80020000 is reread and compared. There should be a cache hit in the secondary cache.

Possible errors:

0104056: Unexpected Cache write through to memory
addr = %x
expected = %x, actual = %x, XOR %x
Seconday TAG %x
0104057: Secondary Cache miss, expected a cache hit
addr = %x
expected = %x, actual = %x, XOR = %x
Data in memory = 0xdeadbeef
Seconday TAG %x

cache36 (sd_dirtywbw) - Secondary Dirty Writeback (Word) Test

This verifies the block (four words) write mode in the data cache. It writes to K0 (0x80020000) cached space, causing the cache become dirty. Then it replace the cache line by reading 0x80022000, which is a different cache line with same offset. This causes the data in 0x80020000 write back to secondary which now has the same data as in 0x80020000. A write to address 0x80060000 will replace the secondary lines, thus forcing a writeback from the Secondary Cache. Note that there is another flavor of this test, d_dirtywbw.c, that forces the writeback from the primary line when the secondary line is replaced.

Possible errors:

0105058: Unexpected Cache write through to memory
addr = %x
expected = %x, actual = %x, XOR %x
Seconday TAG %x
0105059: Data read replaced a dirty line in Secondary
Dirty line not written back to memory
addr = %x
expected = %x, actual = %x, XOR %x
Seconday TAG %x

cache37 (sd_dirtywbh) - Secondary Dirty Writeback (Half-word) Test

This verifies the block (four words) write mode in data cache. It writes to K0 (0x80020000) cached space, causing the cache to become dirty. Then it replaces the cache line by reading 0x80022000, which is a different cache line with same offset. This causes the data in 0x80020000 to be written back to memory which now has the same data as in 0x80020000. Multiple cache lines are tested back to back. Half-word transactions are tested.

Possible errors:

010505a: Unexpected Cache write through to memory on store halfword
addr = %x
expected = %4x, actual = %4x, XOR %4x
Seconday TAG %
010505b: Halfword read replaced a dirty line in Secondary, dirty line not written back to memory
addr = %x
expected = %4x, actual = %4x, XOR %4x
Seconday TAG %x

cache38 (sd_dirtywbb) - Secondary Dirty Writeback (Byte) Test

Possible errors:

010505c: Unexpected Cache write through to memory on store byte
addr = %x
expected = %2x, actual = %2x, XOR %2x
Seconday TAG %x
010505d: Byte read replaced a dirty line in Secondary, dirty line not written back to memory
Dirty line not written back to memory
addr = %x
expected = %2x, actual = %2x, XOR %2x
Seconday TAG %x

cache39 (sd_tagecc) - Secondary TAG ECC Test

This checks the data integrity of the secondary data tag RAM path, using a walking ones/zeros pattern.

Possible errors:

010505e: Secondary Data TAG RAM ECC Path error (walking one as data)
TAG RAM Location 0x%x
Expected 0x%x  Actual= 0x%x  XOR= 0x%x
010505f: Secondary Data TAG RAM ECC Path error (walking zero as data)
TAG RAM Location 0x%x
Expected 0x%x  Actual= 0x%x  XOR= 0x%x

cache40 (sdd_hitinv) - Secondary Hit Invalidate Test

This verifies the Hit Invalidate cache operation.

Possible errors:

0105060: S-cache state error during initialization
addr = %x
expected = %x, actual = %x, XOR %x
Seconday TAG %x
0105061: S-Cache error during Primary Cache dirty line writeback to Scache
0105062: S-Cache state error on a  Hit Invalidate Cache OP
0105063: Data written back to memory after a Hit Invalidate on the Secondary
addr = %x
expected = %x, actual = %x, XOR %x
Seconday TAG %x
0105064: S-Cache state error on a  Hit Invalidate Cache OP
0105065: Primary Cache TAG not invalid after a Hit Invalidate on the Scache
addr %x
Seconday TAG %x
Primary TAG %x
0105066: Data written back to memory after a Hit Invalidate on the Secondary
addr = %x
expected = %x, actual = %x, XOR %x
Seconday TAG %x
Primary TAG %x

For errors 0105061, 0105062, and 0105064, the following additional information is provided:

Error in Secondary Cache TAG State field
      OR Error in Secondary Cache TAG physical tag field
      OR Error in Secondary Cache TAG Virtual Address field
Address 0x%08x\nSecondary TAG Data 0x%08x
Expected Cache State:  0x%x = [STATE]

STATE is one of the decoded cache states: Invalid, Clean Exclusive, Dirty Exclusive, Shared, and Dirty Shared.

cache41 (sd_hitwb) - Secondary Hit Writeback Test

This verifies the hit writeback cache operation. It verifies that the data can be written back from the secondary, or in the case where the primary data is more current, that the data is written from the primary to memory. Also checked is the fact that the cache lines are not invalidated as with the hit writeback invalidate cache operation. Instead, it checks that the lines are set to the clean exclusive state.

Possible errors:

0105067: Initialization error, unexpected Cache write through to memory
addr = %x
expected = %x, actual = %x, XOR %x
Seconday TAG %x
0105068: SCache error during Primary Cache dirty line writeback to Scache
0105069: Data not written back from Scache to Memory on Hit Writeback Cache OP
addr = %x
expected = %x, actual = %x, XOR %x
Seconday TAG %x
010506a: Initialization error, unexpected Cache write through to memory
addr = %x
expected = %x, actual = %x, XOR %x
Seconday TAG %x
010506b: SCache state error during Hit Writeback on S-Cache dirty line
010506c: Error in Primary Cache TAG after a Hit Writeback cache Op on the SCache
addr %x
Expected cache state: Dirty Exclusive
Primary Data TAG %x
010506d: Data not written back from D-Cache to Memory on a Hit Writeback on the S-Cache
addr = %x
expected = %x, actual = %x, XOR %x
Seconday TAG %x
Primary Data TAG %x

For errors 0105068 and 010506b, the following additional information is provided:

Error in Secondary Cache TAG State field
      OR Error in Secondary Cache TAG physical tag field
      OR Error in Secondary Cache TAG Virtual Address field
Address 0x%08x\nSecondary TAG Data 0x%08x
Expected Cache State:  0x%x = [STATE]

STATE is one of the decoded cache states: Invalid, Clean Exclusive, Dirty Exclusive, Shared, and Dirty Shared.

cache42 (sd_hitwbinv) - Secondary Hit Writeback Invalidate Test

This verifies the hit writeback invalidate cache operation. It verifies that the data can be written back from the secondary or in the case where the primary data is more current, that the data is written from the primary to memory. Also checked is that the cache lines are invalidated.

Possible errors:

010506e: Initialization error, unexpected Cache write through to memory
addr = %x
expected = %x, actual = %x, XOR %x
Seconday TAG %x
010506f: S-Cache TAG error after Hit Writeback Invalidate cacheop
0105070: Data not written back from Scache to Memory after Hit Writeback Invalidate Cacheop
addr = %x
expected = %x, actual = %x, XOR %x
Seconday TAG %x
0105071: Initialization error, unexpected Cache write through to memory
addr = %x
expected = %x, actual = %x, XOR %x
Seconday TAG %x
0105072: S-Cache TAG error after Hit Writeback Invalidate cacheop, test case 2
0105073: Error in Primary Cache TAG after a Hit Writeback Invalidate cacheop on the SCache
addr %x
Expected cache state: Invalid
Primary Data TAG %x
0105074: Data not written back from D-Cache to Memory on a Hit Writeback Invalidate on the S-Cache
addr = %x
expected = %x, actual = %x, XOR %x
Seconday TAG %x
Primary Data TAG %x

For errors 010506f and 0105072, the following additional information is provided:

Error in Secondary Cache TAG State field
      OR Error in Secondary Cache TAG physical tag field
      OR Error in Secondary Cache TAG Virtual Address field
Address 0x%08x\nSecondary TAG Data 0x%08x
Expected Cache State:  0x%x = [STATE]

STATE is one of the decoded cache states: Invalid, Clean Exclusive, Dirty Exclusive, Shared, and Dirty Shared.

cache43 (cluster) - Secondary Cluster Test

Possible errors:

0105075: SCache data incorrectly written to memory during a dirty writeback operation
1st mem block
Mem Address 0x%08x
Expected 0x%08x, Actual 0x%08x, XOR 0x%08x
0105076: SCache data incorrectly written to memory during a dirty writeback operation
2nd mem block
Mem Address 0x%08x
Expected 0x%08x, Actual 0x%08x, XOR 0x%08x

cache44 (clusterwb) - Secondary Cluster Writeback Test

Possible errors:

0105077: SCache data incorrectly written to memory during a dirty writeback operation on 1st block
Mem Address 0x%08x
Expected 0x%08x, Actual 0x%08x, XOR 0x%08x
0105078: SCache data incorrectly written to memory during a dirty writeback operation on 2nd block
Mem Address 0x%08x
Expected 0x%08x, Actual 0x%08x, XOR 0x%08x
0105079: SCache data incorrectly written to memory during a dirty writeback operation on 3rd block
Mem Address 0x%08x
Expected 0x%08x, Actual 0x%08x, XOR 0x%08x

cache45 (hammer_pdcache) - Stress Primary D-cache (Runs icached)

Possible error:

010407b: Primary cache stress error at addr : 0x%x Expected 0x%x Got 0x%x

cache46 (hammer_scache) - Stress Secondary Cache (Runs icached)

Possible error:

010507c: Secondary cache stress error at addr : 0x%x Expected 0x%x Got 0x%x

cache47 (cache_stress) - Cache Stress Test

Write/read to one word in every page through 0x80000000 space.

Possible error:

010507a: Secondary cache stress error at addr : 0x%x Expected 0x%x Got 0x%x

cache48 (cache_states) - Complete Cache-State Transitions Test

There are twenty-two individual cache tests. Table 6-8 lists the tests and describes them. The following abbreviations are used in the descriptions:

Clean Exclusive

Dirty Exclusive

Invalid

Table 6-8. Cache State Transition Tests

Cache State Transition Test

Description

cstate0 (RHH_CE_CE)

Read hit primary (CE) and secondary (CE). Check that the value is correct (the physmem addr) and that both tags are still CE.

cstate1 (RHH_DE_DE)

Read hit primary (DE) and secondary (DE). Check value and that both are still DE.

cstate2 (WHH_CE_CE)

Write hit primary (CE) and secondary (CE). Check that secondary and memory still have old value and that both cache lines are now DE.

cstate3 (WHH_DE_DE)

Write hit primary (DE) and secondary (DE). Check that secondary and memory still have old value and that both lines are still DE.

cstate4 (RMH_I_CE)

Read miss primary (I) and hit secondary (CE). Check that secondary and memory still have old value and that both lines are CE.

cstate5 (RMH_I_DE)

Read miss primary (I) and hit secondary (DE). Check that secondary and memory still have old value and that both lines are DE.

cstate6 (RMH_CE_CE)

Read miss primary (CE) and hit secondary (CE). Check that secondary and memory still have old value and that both lines are still CE.

cstate7 (RMH_DE_DE)

Read miss primary (DE) and hit secondary (DE). Check that secondary and memory still have old value and that both lines are still CE.

cstate8 (WMH_I_CE)

Write miss primary (I) and hit secondary (CE). Check that secondary and memory still have old value and that both lines are DE.

cstate9 (WMH_I_DE)

Write miss primary (I) and hit secondary (DE). Check that secondary and memory still have old value and that both lines are DE.

cstate10 (WMH_CE_CE)

Write miss primary (CE) and hit secondary (CE).

cstate11 (WMH_DE_DE)

Write miss primary (DE) and hit secondary (DE).

cstate12 (RMM_I_I)

Read miss primary (I) and secondary (I). Check that value is correct, that secondary and memory still have old value and that both lines are CE.

cstate13 (RMM_I_CE)

Read miss primary (I) and miss secondary (CE). Check that value is correct, that secondary and memory still have old value and that both lines are CE.

cstate14 (RMM_I_DE)

Read miss primary (I) and miss secondary (DE). Check that secondary line matches memory, that both tags are CE, that the addr tags on both lines are correct, and that the dirty altaddr secondary line was flushed to memory.

cstate15 (RMM_CE_CE)

Read miss primary (CE) and miss secondary (CE). Fill cache lines with a word from physaddr+secondarycachesize; do a read, then check that the tags for both lines are CE and have the correct phys addrs, and that the alternate memory word hasn't changed ###.

cstate16 (RMM_DE_DE)

Read miss primary (DE) and miss secondary (DE). Fill cache lines with a word from physaddr+secondarycachesize; do a read, then check that the tags for both lines are now CE and have the correct phys addrs, and that the alternate memory word was written when the altaddr line was flushed.

cstate17 (WMM_I_I)

Write miss primary (I) and secondary (I). Check that secondary line matches memory, that both tags are DE, and that the addr tags on both lines are correct.

cstate18 (WMM_I_CE)

Write miss primary (I) and miss secondary (CE). Check that secondary line matches memory, that both tags are DE, and that the addr tags on both lines are correct.

cstate19 (WMM_I_DE)

Write miss primary (I) and miss secondary (DE). Check that secondary line matches memory, that both tags are DE, that the addr tags on both lines are correct, and that the dirty altaddr secondary line was flushed to memory.

cstate20 (WMM_CE_CE)

Write miss primary (CE) and miss secondary (CE). Fill cache lines with a word from physaddr+secondarycachesize; do a store, then check that the tags for both lines are DE and have the correct phys addrs, and that the alternate memory word hasn't changed.

cstate21 (WMM_DE_DE)

Write miss primary (DE) and miss secondary (DE). Check that secondary line matches memory, that both tags are DE, that the addr tags on both lines are correct, and that the dirty altaddr primary and secondary lines were flushed to memory.

Possible errors:

010707d: RHH_CE_CE : physaddr 0x%x contents incorrect (0x%x)
010707e: RHH_DE_DE : physaddr 0x%x contents incorrect (0x%x)
010707f: RMH_I_CE : physaddr 0x%x contents incorrect (0x%x)
0107080: RMH_I_DE : physaddr 0x%x contents incorrect (0x%x)
0107081: RMH_CE_CE : physaddr 0x%x contents incorrect (0x%x)
0107082: RMH_DE_DE : physaddr 0x%x contents incorrect (0x%x)
0107083: RMM_I_I : physaddr 0x%x contents incorrect (0x%x)
0107084: RMM_I_CE : physaddr 0x%x contents incorrect (0x%x)
0107085: RMM_I_DE : physaddr 0x%x contents incorrect (0x%x)
0107086: PRIMARYD cache state error at addr 0x%x : Expected 0x%x Got 0x%x
     OR  PRIMARYI cache state error at addr 0x%x : Expected 0x%x Got 0x%x
     OR  SECONDAR cache state error at addr 0x%x : Expected 0x%x Got 0x%x
0107087: PRIMARYD addr error at slot 0x%x : Expected 0x%x Got 0x%x
     OR  PRIMARYI addr error at slot 0x%x : Expected 0x%x Got 0x%x
     OR  SECONDARY addr error at slot 0x%x : Expected 0x%x Got 0x%x
0107088: Mem value error at addr 0x%x : Expected 0x%x Got 0x%
0107089: Writeback missed 2ndary level cache at addr 0x%x
010708a: 2ndary cache value error at addr 0x%x : Expected 0x%x Got 0x%x

MC3 IDE Tests

To start an MC3 IDE test, boot IDE from the Command Monitor. See Section 6.2, "Running an IDE Test."

Set the desired report level. The default report level is 2.

Available report levels are shown in Table 6-9

Table 6-9. MC3 Report Levels

Report Level	Function	Comments
Level 5	Displays debugging messages.	Too much detail for most testing scenarios.
Level 4	Prints out memory locations as they are written.	Increases testing time.
Level 3	Prints out one-line functional descriptions within tests.	Probably the most useful level for general testing.
Level 2 (default)	Prints out only errors and titles.	This is the default level.
Level 1	Prints out only titles and pass/fail

Each test level prints out messages for that level and all lower levels.

After setting the report level, choose a test mode (if desired). The following modes are available:

quickmode

For the memory tests, quick mode tests every nth byte instead of every byte, where n varies from 96 to 7680 depending upon the test. The goal in quickmode is to test 16 GB in about 10 minutes, which is accomplished by testing every nth byte. n varies depending upon how fast or slow a test was timed to run.

To enable quickmode, enter

setenv quickmode 1

To disable quickmode, enter

unsetenv quickmode

continue-on-error

Normally, MC3 tests stop after the first error. Enabling continue-on-error mode causes the tests to continue even after an error is encountered.

To enable continue-on-error mode, enter

setenv cont_on_error 1

To disable continue-on-error mode, enter

unsetenv cont_on_error

By default, continue-on-error mode is disabled.

memall

Runs all MC3 diagnostic commands. Can be used in quickmode and in continue-on-error mode.

memquick

Runs only the fastest MC3 diagnostic commands: mem1, mem2, mem3, mem5, mem8, mem9, and mem10. The memquick command can be used in quickmode and in continue-on-error mode.

There are also two special commands to help isolate memory problems in banks:

`ena_bnk`		Enable one bank at a time.
`dis_bnk`		Disable one bank at a time.

Table 6-10 lists and describes the available MC3 diagnostic commands.

Table 6-10. MC3 Tests

Test	Function	Description
mem1	Read the MC3 configuration registers (very fast test) The mem1 test is very similar to the mem14 test, which is the POD DMC command.	This tests reads (probes) the following MC3 configuration registers: 00 - Bank enable 01 - BoardType 02 - RevLevel 03 - AccessControl: endianness subBlockOrder ebus=64bitsOrNot 04 - MemoryErrorInterrupt 05 - EBUSErrorInterrupt 07 - BIST result 07 - DRSC timeout 0a - LeafControlEnable Reads leaf registers 10-24, 30-33 (leaf 0), 50-64, and 70-73 (leaf 1)
mem2	Memory sockets connection test (ported from the IP17 mem1 test; a very fast test)	The memory sockets connection test writes patterns to the first 2 KB of each configured leaf and then reads them back. By writing 2 KB, all simms are ensured of being written to regardless of the interleaving factor specified. If the pattern read back does not match, the socket is assumed to have a connection problem.
mem3	Walking address test (ported from the IP17 mem1 test; a very fast test)	This is a traditional test that checks for shorts and opens on the address lines. Address lines that are greater or equal to the most significant address lines of the memory bounds are not tested. Testing is done by byte read/writes from first_address up to last_address.
mem4	Write/Read data patterns (ported from the IP17 mem3 test) (4 minutes/128 MB)	This test does word read/writes of all-1's and all-0's patterns. It shows if all addresses appear to be writable, and that all bits may be set to both 1 and 0. However, it provides no address error or adjacent-bits-shorted detection. The flow is as follows: (w0), u(r0,w1), d(r1,w5a), u(r5a,ra5), d(ra5) – word and byte (Read as: write 0 to all locations, read 0 and write 1 to all locations in ascending order, read 1 and write 5a to all locations in descending order, read 5a and write a5 to all locations in ascending order, read a5 from all locations in descending order) The mem13 test does byte read/writes in the same pattern. The tests were separated out since the byte read/writes take a long time.
mem5	Address in address memory test (4 minutes/128 MB)	This is a traditional, heuristic, rule-of-thumb, address-in-address memory test. It also puts the complement of the address in the address, and makes passes in both ascending and descending addressing order. There are both full memory store then check passes, as well as read- after-write passes (with complementing).
mem6	Walking ones and zeros memory test (slow; 40 minutes/32 MB)	Another traditional test – walking ones and walking zeros through memory. This is a whole-memory test that is very good at shaking out shorted data bits, but provides little protection for addressing errors.
mem7	March X (4 minutes/128 MB)	Described in van de Goor's book, Testing Semiconductor Memories and has the following flow: (w0), u(r0,w1), d(r1,w0), (r0) Will detect address decoder faults, stuck-at-faults, transition faults, coupling faults, and inversion coupling faults (see van de Goor for definitions).
mem8	March Y (4 minutes/128 MB)	Described in van de Goor's book, Testing Semiconductor Memories and has the following flow: (w0), u(r0,w1,r1), d(r1,w0,r0), (r0) Will detect address decoder faults, stuck-at-faults, transition faults, coupling faults, and linked transition faults (see van de Goor for definitions).
mem9	Memory with ECC test (ported from the IP17 mem6 test) (2 minutes/128 MB)	This test writes to memory via uncached space and reads back through cached space (ECC exceptions enabled). Although it provides a simple level of ECC checking, its main function is to verify that cached and uncached memory addresses are accessing the same area of physical memory. The test values used are address-in-address and inverted address- in-address patterns, so a certain amount of address uniqueness checking is done as well.
mem10	Cache write-through memory test (ported from the IP17 mem9 test) (2 minutes/128 MB)	This is a traditional, heuristic, rule-of-thumb, address-in-address memory test. It also puts the complement of the address in the address, making passes in ascending order only. All of memory is stored and then checked. All reads and writes are made through K0 seg, so the reads and writes are cached. However, since the size of main memory exceeds the cache sizes, all data will be written to main memory and then read back. This is not a particularly thorough test, and it depends upon a good cache to function correctly, but it is fast, at least compared to the other full-memory tests.
mem11	User-specified pattern/location write/read test (ported from the IP17 mem7 test)	Typing `mem11` with no arguments displays a use message: `Usage: mem11 [-b\|h\|w] [-r] [-l] [-v 0xpattern] RANGE`This test is allows the technician to fill a range of memory with a specified test value and read it back, done as a series of byte ( `–b`), half-word ( `–h`), or word ( `–w`) writes and reads. If the `–v` option is not used to select the test pattern, an address-in-address pattern is used instead. ( `–r`) will do read only and will not do any writes. ( `–l`) will loop forever.
mem12	Decode a bad address into a slot, leaf, bank or SIMM number	`Usage: mem12 [-a 0xaddress] [-b xxxxx] [-s x]`–b expects a hex number showing which bits are bad. For example, if bits 1 and 4 are bad, enter: `–b 0x5``–s` 1, 2, or 4 for byte, half-word or word `–b` defaults to 0x0 and `–s` defaults to 4 For example, to decode address 0x4000 with bad bits 1 and 4 and it's a word, type: `mem12 -a 0x4000 -b 0x5 -s 4`
mem13	Byte read/write (slow; 15 minutes/32 MB)	See mem4.
mem14	Read the MC3 configuration registers.	This is the same as the DMC command from POD mode. See also the mem1 command.
mem15	Double-word March Y pattern test (4 mionutes/128 MB)	Same as the mem8 command, but performs double-word writes/reads instead of single-word writes/reads.

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