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Index

32-bit addressing
address size
Defining the Address Space
page size
Page Numbers and Offsets

64-bit addressing
address size
Defining the Address Space
page size
Page Numbers and Offsets

_ABI_SOURCE compiler variable
Two Implementation Versions

address range
Defining the Address Space

address space
Defining the Address Space
Virtual Memory
cannot undefine
Address Definition
copy on write
Normal Process Creation With fork()
copy-on-write pages
Copy-on-Write Pages
defining addresses
Address Definition
duplicated by fork()
Normal Process Creation With fork()
functions that change
Isolating a CPU From TLB Interrupts
heap segment
Address Space Boundaries
interrogating
Interrogating the Memory System
limits of
Address Space Limits
low 4 MB reserved
Segments at a Fixed Address
lowest used address
Address Space Boundaries
of VME bus devices
VME Address Space Mapping
protection
Changing Memory Protection
read-only pages
Read-Only Pages
replaced by exec()
Address Space Replacement With exec()
resident set size
Page Validation
segment
Defining the Address Space
segment reserved for user mapping
Segments at a Fixed Address
shared by lightweight processes
Lightweight Process Creation With sproc()
stack segment
Address Space Boundaries
Probing the Address Space
text segment
Address Space Boundaries
Probing the Address Space
virtual size of
Address Definition
Apparent Process Size

affinity scheduling
Understanding Affinity Scheduling
compared to static assignment
Assigning a Process to a Processor Set

affinity value
Understanding Affinity Scheduling

aio_cancel()
Scheduling Asynchronous I/O

aio_error()
Polling for Status
Checking for Completion
example code
Asynchronous I/O Example

aio_fsync()
Assuring Data Integrity
example code
Asynchronous I/O Example

aio_read()
Scheduling Asynchronous I/O
example code
Asynchronous I/O Example
from callback
Establishing a Callback Function
implies aio_init()
Implicit Initialization

aio_return()
Checking for Completion
example code
Asynchronous I/O Example

aio_sgi_init()
Initializing with aio_sgi_init()
example code
Asynchronous I/O Example

aio_suspend()
Checking for Completion
example code
Asynchronous I/O Example

aio_write()
Scheduling Asynchronous I/O
example code
Asynchronous I/O Example
from callback
Establishing a Callback Function
implies aio_init()
Implicit Initialization

aircraft simulator
Aircraft Simulators

Application Binary Interface. See MIPS ABI
Two Implementation Versions

asynchronous I/O
Asynchronous I/O
Achieving High Transfer Rates to Disk
Asynchronous I/O
aiocb structure
Checking for Completion
Asynchronous I/O Control Block
difference between 5.3 and 5.2
Two Implementation Versions
example code
Asynchronous I/O Example
in IRIX 6.0
Two Implementation Versions
initializing
Initializing Asynchronous I/O
multiple operations to one file
Multiple Operations to One File
not compatible with guaranteed rate
Sharing Access to Guaranteed Files
notification methods
Checking for Completion
POSIX 1003.1b-1993
Two Implementation Versions
request priority no longer supported
Asynchronous I/O Control Block
signal use
Checking for Completion

average data rate
Requirements on Data Collection Systems

backing store
Describing the Source Object
Address Definition
Page Validation
Synchronizing the Backing Store

barrier
Barriers
starting Frame Scheduler
Implementing Synchronized Schedulers

barrier()
Barriers
example code
Asynchronous I/O Example
Asynchronous I/O Example

batch priority
Setting a Nondegrading Batch Priority

brk()
Delayed Definition
Address Definition
modifies address space
Isolating a CPU From TLB Interrupts

bus
processor. See processor bus
CPUs, Memory, and the System Bus

bus,VME. See VME bus
Device Interrupts

cache
address mapping in Challenge/Onyx
Cache Mapping in Challenge/Onyx
affinity scheduling
Understanding Affinity Scheduling
architecture
Memory Hierarchy
effect of miss
Reducing Cache Misses
management
Reducing Cache Misses
multiprocessor conflicts
Multiprocessor Cache Conflicts
warming up in first frame
Process Execution

cache coherency
Cache Coherency Updates

cache line
Reducing Cache Misses

cacheflush()
Isolating a CPU From TLB Interrupts

calloc()
Delayed Definition

CD-ROM audio library
CD-ROM and DAT Audio Libraries

Challenge/Onyx architecture
Symmetric Multiprocessor Architecture
cache address mapping
Cache Mapping in Challenge/Onyx
cache management in
Reducing Cache Misses
PIO error latency
Mapping a VME Device

chkconfig command
Delayed Definition

chmod command
File Integrity

concurrent execution
Concurrent Execution

copy on write page statue
Normal Process Creation With fork()

CPU
assign interrupt to
Assigning Interrupts to CPUs
assign process to
Assigning Work to a Restricted CPU
CPU 0 not used by Frame Scheduler
Frame Scheduler Basics
isolating from sprayed interrupts
Isolating a CPU From Sprayed Interrupts
isolating from TLB interrupts
Isolating a CPU From TLB Interrupts
making nonpreemptive
Making a CPU Nonpreemptive
relation to bus and memory
CPUs, Memory, and the System Bus
restricting to assigned processes
Mapping Processes and CPUs
Restricting a CPU From Scheduled Work

current directory
Process Composition

cycle counter
Hardware Cycle Counter
as Frame Scheduler time base
High-Resolution Timer
drift rate of
Hardware Cycle Counter
Using the Cycle Counter
example program
Mapping and Reading the Cycle Counter
in interval timer management
Timer Management in Challenge, Onyx, and POWER-Challenge
mapping into memory
Using the Cycle Counter
precision of
Using the Cycle Counter
Hardware Cycle Counter
used for timestamp
Using the Cycle Counter

DAT audio library
CD-ROM and DAT Audio Libraries

data collection system
Major Types of Real-Time Programs
Data Collection Systems
average data rate
Requirements on Data Collection Systems
input rate
Achieving High Transfer Rates to Devices
peak data rate
Requirements on Data Collection Systems
requirements on
Requirements on Data Collection Systems

data segment
locking
Locking Program Text and Data

date command
Using the Time of Day

deadline scheduling
Deadline Scheduling
Using Deadline Scheduling

degrading priority
Special Scheduling Disciplines
Aging Priorities

/dev file system
How Devices Are Defined

/dev/ei
External Interrupts

/dev/mem
Mapping Physical Memory

/dev/mmem
Mapping Kernel Virtual Memory

/dev/vme
Mapping a VME Device

/dev/zero
and mmap()
Mapping a Segment of Zeros
Describing the New Segment

device
defined in /dev
How Devices Are Defined
device numbers
How Devices Are Defined
opening
Other I/O
How Devices Are Used

device driver
Interrupt Response Time
Device Interrupts
as Frame Scheduler time base
The Frame Scheduler Device Driver Interface
entry points to
Device Driver Entry Points
for VME bus master
DMA Access to Master Devices
generic SCSI
Generic SCSI Device Driver
in synchronous input
Synchronous Input
reference pages
Device Driver Entry Points
tape
System Tape Device Driver
typical operation of
Device Driver Use

device interrupt
Device Interrupts

device service time
Device Service Time
Interrupt Response Time
Components of Interrupt Response Time
not guaranteed
Service Time for Other Devices

device special file
How Devices Are Defined

direct disk output
Using Direct Writing

disk output
synchronous direct
Using Direct Writing
synchronous unbuffered
Using Synchronous Writing

dispatch cycle time
Components of Interrupt Response Time
Dispatch Cycle

dlopen()
Isolating a CPU From TLB Interrupts

DMA engine for VME bus
DMA Engine Access to Slave Devices
performance
DMA Engine Access to Slave Devices

DMA mapping
DMA Mapping

DMA to VME bus master devices
DMA Access to Master Devices

drift rate of cycle counter
Using the Cycle Counter

dslib
Generic SCSI Device Driver

DSO
Isolating a CPU From TLB Interrupts

DSO, text segment for
Address Space Boundaries

dynamic shared object. See DSO
Isolating a CPU From TLB Interrupts

eicbusywait()
Receiving Interrupts

/etc/autoconfig command
Assigning Interrupts to CPUs

exec()
Address Space Replacement With exec()

external interrupt
External Interrupts
External Interrupts
generate
Generating External Signals
input is edge-triggered
Receiving Incoming External Interrupts
pulse widths
Detecting An External Interrupt
set pulse widths
Setting the Expected Pulse Widths
with Frame Scheduler
External Interrupts

fasthz tuning parameter
Using a Fast Timer Frequency
effect of truncation
Selecting the fasthz Value

fcntl()
example code
Creating a Real-time File

file access permissions and mmap()
File Permissions

file descriptor
of a device
How Devices Are Used
returned by open()
Other I/O
with asynchronous I/O
Asynchronous I/O Control Block
with guaranteed-rate I/O
Requesting a Guarantee
with mmap()
Describing the Source Object

file, mapping into memory
Locking Mapped Files Into Memory
Mapping a File for I/O

fork()
Normal Process Creation With fork()
defines address space
Address Definition
example
Normal Process Creation With fork()
example code
Code of Basic Example
new address space copy-on-write
Copy-on-Write Pages
rate guarantee not inherited
Sharing Access to Guaranteed Files

frame interval
Frame Rate

frame rate
Frame Rate
of plant control simulator
Plant Control Simulators
of virtual reality simulator
Virtual Reality Simulators

Frame Scheduler
REACT/Pro Frame Scheduler
Using the Frame Scheduler
advantages
Advantages of the Frame Scheduler
and cycle counter
High-Resolution Timer
and external interrupt
External Interrupts
and R4000 timer
On-Chip Timer Interrupt
and vertical sync
Vertical Sync Interrupt
background discipline
Background Discipline
continuable discipline
Continuable Discipline
CPU 0 not used by
Frame Scheduler Basics
definition of frame
How Frames Are Defined
design process
Designing With the Frame Scheduler
device driver initialization
Frame Scheduler Initialization Function
device driver interface
The Frame Scheduler Device Driver Interface
device driver interrupt
Generating Interrupts
device driver termination
Frame Scheduler Termination Function
device driver use
Device Driver Overview
example code
Frame Scheduler Examples
exception handling
Handling Frame Scheduler Exceptions
frs-master process
Using Multiple Synchronized Schedulers
Frame Scheduling
frs_run flag
Scheduler Flags frs_run and frs_yield
frs_yield flag
Scheduler Flags frs_run and frs_yield
interface to
The Frame Scheduler API
interval timers not used with
Using Timers with the Frame Scheduler
major frame
Frame Scheduling
minor frame
Frame Scheduling
multiple synchronized
Using Multiple Synchronized Schedulers
overrun exception
Exception Types
Realtime Discipline
overrunnable discipline
Overrunnable Discipline
pausing
Pausing Frame Schedulers
process outline for multiple
Implementing Synchronized Schedulers
process outline for single
Implementing a Single Frame Scheduler
process structure
Process Execution
realtime discipline
Realtime Discipline
scheduling disciplines
Using the Scheduling Disciplines
scheduling rules of
Scheduling Within a Minor Frame
signals produced by
Setting Frame Scheduler Signals
Handling Frame Scheduler Signals
software interrupt to
Software Interrupt
starting up
Starting the Schedulers
time base selection
How Frames Are Defined
Selecting a Time Base
underrun exception
Realtime Discipline
Exception Types
underrunable discipline
Underrunable Discipline
using consecutive minor frames
Using Multiple Consecutive Minor Frames
warming up cache
Process Execution

frs-master process
Using Multiple Synchronized Schedulers
Frame Scheduling
design of
Implementing a Single Frame Scheduler
receives signals
Setting Frame Scheduler Signals

frs_create_master()
Implementing Synchronized Schedulers
Implementing a Single Frame Scheduler
Exporting the Initialization and Termination Functions
example code
Code of Basic Example

frs_create_slave()
Implementing Synchronized Schedulers

frs_destroy()
Implementing a Single Frame Scheduler
Implementing Synchronized Schedulers
Implementing Synchronized Schedulers
causes SIGHUP
Setting Frame Scheduler Signals
example code
Code of Basic Example

frs_driver_export()
Exporting the Initialization and Termination Functions

frs_enqueue()
Scheduling Within a Minor Frame
Using the Scheduling Disciplines
Implementing a Single Frame Scheduler
Implementing Synchronized Schedulers
Implementing Synchronized Schedulers
example code
Code of Basic Example
Code of Basic Example

frs_handle_driverintr()
Generating Interrupts

frs_join()
Implementing a Single Frame Scheduler
Implementing Synchronized Schedulers
Process Execution
Implementing Synchronized Schedulers
Starting the Schedulers
example code
Code of Basic Example
Code of Basic Example

frs_resume()
Pausing Frame Schedulers

frs_setattr()
example code
Setting Exception Policies
Setting Exception Policies

frs_start()
Implementing Synchronized Schedulers
Starting the Schedulers
Implementing Synchronized Schedulers
Implementing a Single Frame Scheduler
example code
Code of Basic Example

frs_stop()
Pausing Frame Schedulers

frs_userinter()
Software Interrupt

frs_yield
Process Execution

frs_yield()
example code
Code of Basic Example
Code of Basic Example
with overrunable discipline
Overrunnable Discipline

fsync()
Using Synchronous Writing
Synchronous Output

ftruncate() on memory-mapped file
File Integrity

gang scheduling
Using Gang Scheduling
Gang Scheduling

getpagesize()
Page Numbers and Offsets
Interrogating the Memory System

getrlimit()
Address Space Limits

gettimeofday()
Using the Time of Day
Time of Day Timestamp
example code
Getting the Time of Day Stamp

GRIO. See guaranteed-rate I/O
Guaranteed-Rate I/O

grio_remove_request()
Releasing a Guarantee

grio_request()
Requesting a Guarantee
example code
Guaranteed-Rate Request

ground vehicle simulator
Ground Vehicle Simulators

group ID
Process Composition

guaranteed-rate I/O
Achieving High Transfer Rates to Disk
Guaranteed-Rate I/O
creating a real-time file
Creating a Real-time File
example code
Guaranteed-Rate Request
hard guarantee
Hard Guarantees
requesting a guarantee
Requesting a Guarantee
requires XFS
Guaranteed-Rate I/O Basics
requires XLV volume
Guaranteed-Rate I/O Basics
soft guarantee
Soft Guarantees
tied to PD and I-node
Sharing Access to Guaranteed Files
video on demand guarantee
Video On Demand (VOD) Guarantees

hardware latency
Hardware Latency
Components of Interrupt Response Time

hardware simulator
Hardware-in-the-loop (HITL) Simulators

heap segment
Address Definition
Address Space Boundaries

HZ value in timer management
Timer Management Without a Clock Comparator

inline functions and cache management
Locality of Reference

input
synchronous
Synchronous Input

interchassis communication
Interchassis Communication

interprocess communication
Interprocess Communication

interrupt
assign to CPU
Assigning Interrupts to CPUs
clock comparator
Timer Management in Challenge, Onyx, and POWER-Challenge
controlling distribution of
Controlling Interrupt Distribution
device
Device Interrupts
external. See external interrupt
External Interrupts
group. See interrupt group
Selecting a Time Base
isolating CPU from
Isolating a CPU From Sprayed Interrupts
latency
Interrupt Latency
periodic timer
Timer Management Without a Clock Comparator
propogation delay
Hardware Latency
response time. See interrupt response time
Minimizing Interrupt Response Time
spraying
Isolating a CPU From Sprayed Interrupts
Device Interrupts
TLB
Isolating a CPU From TLB Interrupts
Translation Lookaside Buffer Updates
validity fault
Page Validation
vertical sync
Vertical Sync Interrupt
Understanding the Vertical Sync Interrupt
VME bus
Device Interrupts
Hardware Latency

interrupt group
Selecting a Time Base
Frame Scheduler passes to device driver
Frame Scheduler Initialization Function
not used with cycle counter
High-Resolution Timer
to distribute external interrupt
External Interrupts
to distribute vertical sync
Vertical Sync Interrupt

interrupt response time
Minimizing Interrupt Response Time
Interrupt Response Time
200 microsecond guarantee
Maximum Response Time Guarantee
components
Components of Interrupt Response Time
device service not guaranteed
Service Time for Other Devices
device service time
Device Service Time
dispatch cycle
Dispatch Cycle
hardware latency
Hardware Latency
kernel service not guaranteed
Kernel Critical Sections
restrictions on processes
Kernel Critical Sections
software latency
Software Latency

interrupts
unavoidable from timer
Unavoidable Timer Interrupts

interval timer
Timer Interrupts (Itimers)
Using Interval Timers
cycle counter used to manage
Timer Management in Challenge, Onyx, and POWER-Challenge
example
Interprocess Communication
Using an Itimer
management by kernel
How Timers Are Managed
not used with Frame Scheduler
Using Timers with the Frame Scheduler
Timer Interrupts (Itimers)

ioctl()
and device driver
Device Driver Entry Points
generate external signal
Generating External Signals
receive external signal
Receiving Interrupts
set external pulse widths
Setting the Expected Pulse Widths

IPL statement
Assigning Interrupts to CPUs

IRIS InSight
About This Guide

IRIX
kernel
CPUs, Memory, and the System Bus

IRIX overview
Basic Features of the CHALLENGE and IRIX™ Architectures

irix.sm configuration file
Assigning Interrupts to CPUs

itimer. See interval timer
Timer Interrupts (Itimers)

kernel
address space limits in
Address Space Limits
affinity scheduling
Understanding Affinity Scheduling
critical section
Kernel Critical Sections
deadline scheduling
Using Deadline Scheduling
degrading priority
Aging Priorities
gang scheduling
Using Gang Scheduling
interrupt response time
Software Latency
multiprocessor use
CPUs, Memory, and the System Bus
Concurrent Execution
optimizations in
Kernel Optimizations
originates signals
Signals
priority assignment
Priorities
process management
Process Composition
real-time features
Kernel Facilities for Real-Time Programs
scheduling
Scheduling Concepts
scheduling assumptions
Process Scheduling
scheduling queues
Scheduler Queues
tick
Tick Interrupts
time slice
Tick Interrupts
timer management
How Timers Are Managed

kernel address space
Defining the Address Space

latency
hardware
Components of Interrupt Response Time
Hardware Latency
software
Software Latency
Components of Interrupt Response Time

lightweight process
and mapped segments
Describing the New Segment
created with sproc()
Lightweight Process Creation With sproc()
less work to create
Lightweight Process Creation With sproc()
preferred for real-time use
Lightweight Process Creation With sproc()

limits command
Address Space Limits

linked lists and cache management
Locality of Reference

lio_listio()
Scheduling Asynchronous I/O

Locality of Reference
Locality of Reference
Memory Hierarchy

lock
Locks
defined
Locks
effect of gang scheduling
Using Gang Scheduling
metering
Locks
set by spinning
Locks
used by kernel
Concurrent Execution

lockf() to protect mapped file
File Integrity

locking virtual memory
Locking Virtual Memory

lseek()
for file size
Mapped File Sizes
with asynchronous I/O
Asynchronous I/O Control Block
with guaranteed-rate I/O
Video On Demand (VOD) Guarantees

madvise()
Releasing Unneeded Pages

major device number
How Devices Are Defined

major frame
Frame Scheduling

malloc()
Delayed Definition
Address Definition
used to find limit of swap
Delayed Definition

MAP_AUTOGROW flag
Describing the New Segment
Mapping a Segment of Zeros
Isolating a CPU From TLB Interrupts
Describing the New Segment
Describing the New Segment

MAP_FIXED flag
Segments at Fixed Offsets
Segments at a Fixed Address
Choosing a Segment Address
Mapping Portions of a File

MAP_LOCAL flag
Isolating a CPU From TLB Interrupts
Describing the New Segment
Describing the New Segment

MAP_PRIVATE flag
Describing the New Segment
File Integrity

MAP_SHARED flag
File Integrity
Describing the New Segment

memalign()
Locality of Reference

memory
Managing Virtual Memory in a Real–Time Program
address ranges of
Defining the Address Space
backing store for
Address Definition
hierarchy
Memory Hierarchy
interrogating size of
Interrogating the Memory System
locking pages in
Locking Pages in Memory
main
CPUs, Memory, and the System Bus
page
Page Numbers and Offsets
page size
Virtual Memory
protection
Changing Memory Protection
segment
Defining the Address Space
shared. See shared memory
Shared Memory Segments
virtual
Virtual Memory
ZZZ
Mapping Segments of Memory

memory mapping
Mapping Segments of Memory
Address Definition
and file access permissions
File Permissions
at fixed addresses
Segments at a Fixed Address
choosing segment address for
Choosing a Segment Address
conflicts with normal file access
File Integrity
for I/O
Memory-Mapped I/O
Mapping a File for I/O
locking mapped file
Locking Mapped Files Into Memory
mandatory file locks with
File Integrity
of cycle counter
Using the Cycle Counter
of kernel memory
Mapping Kernel Virtual Memory
of NFS-mounted file
NFS Considerations
of physical memory
Mapping Physical Memory
of segment of zeros
Mapping a Segment of Zeros
of VME device
Mapping a VME Device
private copy of file
File Integrity
replacing a mapped segment
Mapping Portions of a File
to create shared segments
Mapping a File for Shared Memory
when pages are defined
Describing the New Segment

metering lock use
Locks

metering semaphore use
IRIX Semaphores

minor device number
How Devices Are Defined

minor frame
Frame Scheduling
Scheduling Within a Minor Frame

MIPS ABI
asynchronous I/O
Two Implementation Versions
reserved address space
Segments at a Fixed Address

mmap()
The Segment Mapping Function mmap()
Isolating a CPU From TLB Interrupts
and file permissions
File Permissions
and NFS-mounted files
NFS Considerations
example code
Mapping and Reading the Cycle Counter
Probing the Address Space
in place of lseek()
Mapping Portions of a File
of /dev/mem
Mapping Physical Memory
of /dev/mmem
Mapping Kernel Virtual Memory
of /dev/vme/*
Mapping a VME Device
of zero segment
Mapping a Segment of Zeros
parameters of
Describing the Source Object
using specified addresses
Segments at a Fixed Address
when swap is allocated
Describing the New Segment

mpadmin command
assign clock processor
Assigning the Clock Processor
make CPU nonpreemptive
Making a CPU Nonpreemptive
query fasthz CPU
Assigning the fasthz Processor
restrict CPU
Restricting a CPU From Scheduled Work
set fasthz CPU
Assigning the fasthz Processor
unrestrict CPU
Restricting a CPU From Scheduled Work

mpin()
Locking Functions
Locking Mapped Files Into Memory

mprotect()
Changing Memory Protection
Isolating a CPU From TLB Interrupts
example code
Probing the Address Space

msync()
Mapping a File for I/O
Synchronizing the Backing Store
NFS Considerations

multiprocessor architecture
CPUs, Memory, and the System Bus
affinity scheduling
Understanding Affinity Scheduling
and Frame Scheduler
Using Multiple Synchronized Schedulers

munmap()
Isolating a CPU From TLB Interrupts

munpin()
Locking Mapped Files Into Memory
Locking Functions

mutual exclusion primitive
Mutual Exclusion Primitives

NDPHIMAX constant
Priorities

NDPHIMIN constant
Priorities

ndpri_hilim tuning parameter
Setting a Nondegrading Batch Priority

ndpri_lolim tuning parameter
Setting a Nondegrading Real-Time Priority

newbarrier()
Barriers

NFS and memory-mapped files
NFS Considerations

“nice” value
Priorities

NOINTR statement
Isolating a CPU From Sprayed Interrupts

nondegrading batch priority
Setting a Nondegrading Batch Priority

nondegrading priorities
Nondegrading Priorities

nondegrading real-time priority
Setting a Nondegrading Real-Time Priority

npri command
Setting a Nondegrading Batch Priority
deadline scheduling
Using Deadline Scheduling
nondegrading priority
Setting a Nondegrading Real-Time Priority

open()
Other I/O
Describing the Source Object
example code
Creating a Real-time File
of /dev/zero
Mapping a Segment of Zeros
of /dev/zero example code
Probing the Address Space
of a device
How Devices Are Used

operator
affected by transport delay
Transport Delay
in virtual reality simulator
Virtual Reality Simulators
of simulator
Simulators

output
synchronous
Synchronous Output
to disk is buffered
Using Synchronous Writing

overrun in data collection system
Requirements on Data Collection Systems

overrun in Frame Scheduler
Realtime Discipline

page
copy on write
Copy-on-Write Pages
locking
Locking Pages in Memory
read-only
Read-Only Pages
releasing unneeded
Releasing Unneeded Pages

page fault
Virtual Memory
causes TLB interrupt
Isolating a CPU From TLB Interrupts
prevent by locking memory
Locking Virtual Memory
Locking Pages in Memory

page size
Virtual Memory
Page Numbers and Offsets

page validation
Page Validation

peak data rate
Requirements on Data Collection Systems

performance effects of cache
Reducing Cache Misses

performance tools
Detecting Cache Problems

PIO access to VME devices
PIO Access

PIO address mapping
PIO Address Space Mapping

pixie command
Detecting Cache Problems

plant control simulator
Plant Control Simulators

plock()
Locking Functions
example of
Locking Program Text and Data

poll()
IRIX Semaphores

power plant simulator
Plant Control Simulators

prctl()
Interrogating the Memory System

priority
Priorities
degrading
Special Scheduling Disciplines
Aging Priorities
looping process can halt system
Setting a Nondegrading Real-Time Priority
nondegrading
Nondegrading Priorities
nondegrading batch
Setting a Nondegrading Batch Priority
nondegrading real-time
Setting a Nondegrading Real-Time Priority
ranges of
Priorities

process
Process Management
”nice” value
Priorities
address space
Address Space Boundaries
assign to CPU
Assigning Work to a Restricted CPU
assigned to processor
Assigning a Process to a Processor Set
attributes
Process Composition
attributes initialized by exec()
Address Space Replacement With exec()
blocked by I/O
I/O Scheduling
composition
Process Composition
created with fork()
Normal Process Creation With fork()
frs-master
Frame Scheduling
lightweight. See lightweight process
Lightweight Process Creation With sproc()
mapping to CPU
Mapping Processes and CPUs
priority of
Priorities
time slice
Time Slices

process control
Major Types of Real-Time Programs

process creation
Process Creation

process group
Gang Scheduling
and gang scheduling
Using Gang Scheduling

process ID
Process Composition
identifies rate guarantee
Sharing Access to Guaranteed Files

process scheduling
Process Scheduling

processor bus
capacity
CPUs, Memory, and the System Bus
diagram
Symmetric Multiprocessor Architecture

processor set
Processor Sets
Using Processor Sets
contradiction
Processor Set Contradictions

prof command
Detecting Cache Problems

propogation delay. See hardware latency
Hardware Latency

ps command
Address Definition

pset command
Scheduler Queues
Using Processor Sets
and restricted CPU
Restricting a CPU From Scheduled Work
contradictions
Processor Set Contradictions

punlock()
Locking Functions

queue, scheduling
Scheduler Queues
Priorities

R4000 timer
On-Chip Timer Interrupt

REACT
About This Guide

REACT/Pro
About This Guide

read()
and device driver
Device Driver Entry Points
synchronous
Synchronous Input
with guaranteed-rate I/O
Requesting a Guarantee

real-time priority
Setting a Nondegrading Real-Time Priority

real-time program
and Frame Scheduler
REACT/Pro Frame Scheduler
and scheduler assumptions
Process Scheduling
data collection
Data Collection Systems
Major Types of Real-Time Programs
defined
Defining Real-Time Programs
disk I/O by
Optimizing Disk I/O for a Real-Time Program
frame rate
Requirements on Simulators
lightweight processes preferred
Lightweight Process Creation With sproc()
process control
Major Types of Real-Time Programs
simulator
Major Types of Real-Time Programs
Simulators
types of
Real-Time Programs

reflective shared memory
Reflective Shared Memory

resident set size
Page Validation

response time. See interrupt response time
Minimizing Interrupt Response Time

restricting a CPU
Restricting a CPU From Scheduled Work

rlimit kernel parameter
Address Space Limits

rtnetd daemon, priority of
Setting a Nondegrading Real-Time Priority

runon command
Assigning Work to a Restricted CPU

schedctl()
Assigning Work to a Restricted CPU
Setting a Nondegrading Real-Time Priority
Setting a Nondegrading Batch Priority
Using Deadline Scheduling
Using Gang Scheduling
example code
Setting a Nondegrading Batch Priority
Setting a Nondegrading Real-Time Priority
Deadline Scheduling Subroutines
Using Gang Scheduling
with Frame Scheduler
The Frame Scheduler API

scheduling
Scheduling Concepts
affinity type
Understanding Affinity Scheduling
assumptions
Process Scheduling
deadline type
Using Deadline Scheduling
Deadline Scheduling
degrading priority
Special Scheduling Disciplines
gang type
Gang Scheduling
Using Gang Scheduling
nondegrading priority
Nondegrading Priorities

scheduling discipline
Assigning a Discipline to a Processor Set
ZZZ
Using the Scheduling Disciplines

scheduling queue
Scheduler Queues
Priorities
processor set assigned to
Assigning a Processor Set to a Queue

SCSI interface
SCSI Devices
generic device driver
Generic SCSI Device Driver

segment
Defining the Address Space
heap
Address Space Boundaries
locking
Locking Program Text and Data
lowest address
Address Space Boundaries
shared
Mapping a File for Shared Memory
stack
Address Space Boundaries
text
Address Space Boundaries

segment address
Choosing a Segment Address

segments at fixed offsets
Segments at Fixed Offsets

semaphore
Semaphores
defined
Semaphores
IRIX implementation
IRIX Semaphores
metering
IRIX Semaphores
pollable
IRIX Semaphores
portable implementation
SVR4-Compatible Semaphores
used by kernel
Concurrent Execution
used with interval timer
Using an Itimer

semget()
SVR4-Compatible Semaphores

semop()
SVR4-Compatible Semaphores

setitimer()
Using Interval Timers
Timer Interrupts (Itimers)
example code
Interprocess Communication

setitimer()example code
Using an Itimer

setrlimit()
Address Space Limits
limit malloc() use
Delayed Definition

sginap()
Locks
example code
Interprocess Communication
Asynchronous I/O Example

shared memory
Shared Memory Segments
IRIX implementation
IRIX Shared Memory Arenas
portable implementation
SVR4-Compatible Shared Memory
reflective
Reflective Shared Memory
usconfig()
IRIX Shared Memory Arenas
usinit()
IRIX Shared Memory Arenas

shared memory segment
Mapping a File for Shared Memory

shmat()
SVR4-Compatible Shared Memory

shmctl()
Isolating a CPU From TLB Interrupts
SVR4-Compatible Shared Memory

shmget()
SVR4-Compatible Shared Memory
SVR4-Compatible Shared Memory
Isolating a CPU From TLB Interrupts

sigaction()
example code
Asynchronous I/O Example
Using an Itimer
Interprocess Communication
with asynchronous I/O
Establishing a Completion Signal

sigaddset()
example code
Interprocess Communication

SIGALRM
from interval timer
Timer Interrupts (Itimers)

SIGBUS
on access to truncated mapped file
File Integrity
on NFS error in mapped file
NFS Considerations
on PIO access to invalid bus address
Mapping a VME Device
Mapping a VME Device
on reference past end of mapped segment
The Segment Mapping Function mmap()
on reference to undefined page
Address Definition

sigemptyset()
example code
Interprocess Communication

sigevent structure
Asynchronous I/O Control Block

SIGHUP
when Frame Scheduler terminates
Setting Frame Scheduler Signals

SIGKILL
on reaching limit of virtual swap
Delayed Definition
possible when locking pages
Locking Functions

signal
Signals
delivery priority
Signals
generated from interval timer
Using Interval Timers
generated in asynchronous I/O
Checking for Completion
latency
Signal Delivery and Latency
SIGALRM
Timer Interrupts (Itimers)
SIGBUS
Mapping a VME Device
Address Definition
NFS Considerations
File Integrity
The Segment Mapping Function mmap()
SIGHUP
Setting Frame Scheduler Signals
SIGKILL
Delayed Definition
Locking Functions
signal numbers
Signals
SIGSEGV
Read-Only Pages
Describing the New Segment
Changing Memory Protection
SIGUSR1
Setting Frame Scheduler Signals
SIGUSR2
Setting Frame Scheduler Signals
with Frame Scheduler
Using Signals Under the Frame Scheduler

signal handler
as process attribute
Process Composition
when setting up Frame Scheduler
Implementing a Single Frame Scheduler
Implementing Synchronized Schedulers
Implementing Synchronized Schedulers

signal()
example code
Code of Basic Example
Code of Basic Example

SIGSEGV
on access to read-only page
Changing Memory Protection
on attempt to change read-only page
Read-Only Pages
on store past end of mapped segment
Describing the New Segment

sigsuspend()
Checking for Completion

SIGUSR1
on underrun
Setting Frame Scheduler Signals

SIGUSR2
on overrun
Setting Frame Scheduler Signals

sigwait()
Checking for Completion

simulator
Simulators
Major Types of Real-Time Programs
aircraft
Aircraft Simulators
control inputs to
Simulators
Plant Control Simulators
frame rate of
Plant Control Simulators
Requirements on Simulators
ground vehicle
Ground Vehicle Simulators
hardware
Hardware-in-the-loop (HITL) Simulators
operator of
Simulators
plant control
Plant Control Simulators
state display
Simulators
virtual reality
Virtual Reality Simulators
world model in
Simulators

sockets
Socket Programming

software latency
Software Latency
Components of Interrupt Response Time

spin lock
Locks

sproc()
Lightweight Process Creation With sproc()
and mapped segments
Describing the New Segment
CPU assignment inherited
Assigning Work to a Restricted CPU
example code
Interprocess Communication
modifies address space
Isolating a CPU From TLB Interrupts
rate guarantee not inherited
Sharing Access to Guaranteed Files

sprocsp()
Isolating a CPU From TLB Interrupts
example code
Asynchronous I/O Example

stack segment
Address Definition
Address Space Boundaries
locking
Locking Program Text and Data

striped volume
Video On Demand (VOD) Guarantees

structures and cache management
Locality of Reference

swap
Page Validation
Address Definition

swapctl()
Interrogating the Memory System

synchronous disk output
Using Synchronous Writing

sys/param.h
Tick Interrupts

sys/schedctl.h
Priorities

sysconf()
Interrogating the Memory System

sysmp()
Assigning Work to a Restricted CPU
Interrogating the Memory System
assign process to CPU
Assigning Work to a Restricted CPU
example code
Assigning the Clock Processor
Restricting a CPU From Scheduled Work
Assigning the fasthz Processor
Assigning Work to a Restricted CPU
Making a CPU Nonpreemptive
Restricting a CPU From Scheduled Work
isolate TLB interrupts
Isolating a CPU From TLB Interrupts
make CPU nonpreemptive
Making a CPU Nonpreemptive
number of CPUs
Restricting a CPU From Scheduled Work
restrict CPU
Restricting a CPU From Scheduled Work
Restricting a CPU From Scheduled Work
run process on any CPU
Assigning Work to a Restricted CPU
set fasthz CPU
Assigning the fasthz Processor

syssg i()
Interrogating the Memory System

syssgi()
Using the Cycle Counter

systune command
Fast Timers Prior to IRIX 5.3

tape device
System Tape Device Driver

telemetry
Major Types of Real-Time Programs

test_and_set
Mutual Exclusion Primitives

text segment
Address Space Boundaries
loaded from program file
Page Validation
locking
Locking Program Text and Data
read-only
Read-Only Pages

tick
Tick Interrupts
disabling
Making a CPU Nonpreemptive

time base for Frame Scheduler
Selecting a Time Base

time slice
Tick Interrupts

timer interrupts unavoidable
Unavoidable Timer Interrupts

timer management
How Timers Are Managed

timestamp
Timestamps
Using Timestamps
comparing methods
Comparing the Timestamps
from cycle counter
Using the Cycle Counter
from gettimeofday()
Using the Time of Day

TLB
Translation Lookaside Buffer Updates

TLB update interrupt
Translation Lookaside Buffer Updates
Isolating a CPU From TLB Interrupts

translation lookaside buffer. See TLB
Translation Lookaside Buffer Updates

transport delay
Transport Delay

udmalib
DMA Engine Access to Slave Devices

underrun, in Frame Scheduler
Realtime Discipline

uscalloc()
example code
Interprocess Communication

usconfig()
IRIX Shared Memory Arenas
example code
Interprocess Communication

usctlsema()
example code
Interprocess Communication

usdetach()
example code
Interprocess Communication
Interprocess Communication

usdumplock()
example code
Interprocess Communication

usdumpsema()
example code
Interprocess Communication

user ID
Process Composition

usgetinfo()
example code
Interprocess Communication
Interprocess Communication

usinit()
IRIX Shared Memory Arenas
arena for barrier
Barriers
arena for lock
Locks
arena for semaphore
IRIX Semaphores
example code
Interprocess Communication

usnewlock()
Locks
example code
Interprocess Communication

usnewsema()
IRIX Semaphores
example code
Interprocess Communication

uspsema
IRIX Semaphores

uspsema()
example code
Interprocess Communication
Asynchronous I/O Example
Interprocess Communication

usputinfo()
example code
Interprocess Communication

ussetlock()
Locks
example code
Interprocess Communication
Interprocess Communication

usunsetlock()
Locks
example code
Interprocess Communication
Interprocess Communication

usvsema
IRIX Semaphores

usvsema()
example code
Interprocess Communication
Interprocess Communication
Asynchronous I/O Example
Using an Itimer

validity fault
Page Validation

vertical sync interrupt
Understanding the Vertical Sync Interrupt
Vertical Sync Interrupt

video on demand (VOD). See guaranteed-rate I/O, video on demand
Video On Demand (VOD) Guarantees

virtual address space. See address space
Defining the Address Space

virtual memory
Virtual Memory
loading pages
Page Validation
locking
Locking Virtual Memory
page fault
Virtual Memory
synchronizing backing store
Synchronizing the Backing Store
ZZZ
Managing Virtual Memory in a Real–Time Program

virtual page number
Page Numbers and Offsets

virtual reality simulator
Virtual Reality Simulators

virtual size
Address Definition

virtual swap
Delayed Definition
SIGKILL from
Delayed Definition
ZZZ
Delayed Definition

VME bus
The VME Bus
address space mapping
VME Address Space Mapping
and process scheduling
VME Bus I/O
assign interrupt to CPU
Assigning Interrupts to CPUs
configuration
VME Bus Attachments
data input rate
Achieving High Transfer Rates to Devices
DMA mapping
DMA Mapping
DMA to master devices
DMA Access to Master Devices
hardware latency of
Hardware Latency
interrupt levels
Device Interrupts
performance
PIO Access
DMA Engine Access to Slave Devices
DMA Access to Master Devices
PIO access
PIO Access
PIO address mapping
PIO Address Space Mapping
udmalib
DMA Engine Access to Slave Devices

VME PIO
Mapping a VME Device

VPN. See virtual page number
Page Numbers and Offsets

write()
and device driver
Device Driver Entry Points
direct
Using Direct Writing
synchronous
Synchronous Output
Using Synchronous Writing
with guaranteed-rate I/O
Creating a Real-time File
Requesting a Guarantee

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Glossary