List of Figures

| Table of Contents | List of Figures | List of Tables |

Figure 1-1. Reconfigurable Computer

Figure 1-2. Bitstream Development

Figure 1-3. Bitstream Development with High-level Tools

Figure 1-4. RASC FPGA Functional Block Diagram

Figure 1-5. RASC Blade Hardware

Figure 1-6. RASC Software Overview

Figure 2-1. Example of SGI Altix 350 Rack Systems

Figure 2-2. Altix 4700 Blade, Individual Rack Unit, and Rack

Figure 3-1. Block Diagram of the RASC Core Services

Figure 3-2. Algorithm Defined Registers (ADR) Interface Usage

Figure 3-3. Start of Input Stream Transaction

Figure 3-4. End of Input Stream Transaction

Figure 3-5. Start of Output Stream Transaction

Figure 3-6. End of Output Stream Transaction

Figure 3-7. SRAM Read Operation

Figure 3-8. SRAM Read with Busy

Figure 3-9. SRAM Write with Busy Assertion

Figure 3-10. Example of a Continuous, Normal Mode Algorithm Run

Figure 3-11. Hardware Accelerated Algorithm Design Flow

Figure 3-12. Clock Cycle Stepping Mode Example

Figure 3-13. Variable Step Size Mode Example

Figure 3-14. Single, and Multiple Write Commands

Figure 3-15. Single Read Transaction

Figure 3-16. Multiple Read Transaction

Figure 3-17. Instance Hierarchy of the RASC FPGA Design

Figure 3-18. Core Clock and Algorithm Clock Source

Figure 3-19. Sample vcdplus.vpd Waveform in Virsim

Figure 4-1. Abstraction Layer Software Block Diagram

Figure 7-1. RASC FPGA Implementation Flow

Figure 8-1. SGI RASC Algorithm Configuration Tool Welcome Screen

Figure 8-2. Algorithm Name Configuration

Figure 8-3. Algorithm Clock Rate Configuration

Figure 8-4. Streaming DMA Configuration

Figure 8-5. Memory Configuration Selection

Figure 8-6. Memory Port Specification

Figure 8-7. Number of Algorithm Defined Register Selection

Figure 8-8. Algorithm Defined Register Specification

Figure 8-9. Number of Debug Registers Selection

Figure 8-10. Synthesis Tool Specification

Figure 8-11. Supplemental Algorithm Clock Configuration

Figure 8-12. Overwrite of alg_block_top.v Verification

Figure 8-13. Write-Protect File Notification

Figure 10-1. Simple Algorithm for Verilog

Figure 10-2. Simple Algorithm for Verilog andVHDL

Figure 10-3. Simple Algorithm for Verilog and VHDL

Figure 10-4. Data Flow Algorithm

Figure 10-5. Streaming DMA Algorithm