Streaming Direct Memory Access (DMA)

SGI Core Services provide four input and four output streaming DMA engines that allow data to transfer directly into the FPGA. These are individually selectable and you may select them in any combination. A new strm_in_<n>_complete signal also allows you to input data in chunks so you do not have to read or write an entire DMA length. You can use the new SGI RASC Algorithm Configuration tool described in Chapter 8, “SGI RASC Algorithm Configuration Tool” to configure these streams. For more information, see “Streaming DMA Configuration” in Chapter 8.

Memory

Three memory configurations instead of just one are available. As in prior releases, two 64-bit memory ports are paired up to be used as a 128-bit memory with a fifth 64-bit memory port available. The RASC 2.20 release provides a new configuration that enables five 64-bit memory ports. All five of these ports are independent and can be configured individually. Each memory port can be configured to only allow access by the algorithm to reduce logic overhead. You can also choose to have no external memory ports at all. Memory configuration is described in “Memory Configuration” in Chapter 8.

Algorithm Defined Registers (ADRs)

The SGI Core Services provides up to sixty-four (64) 64-bit registers to handle the communication between the host program and the algorithm. The number of registers is now selectable. For more information, see “Algorithm Defined Registers” in Chapter 8. The algorithm defined registers can also be further specified for usage, as described in “Algorithm Defined Register Configuration” in Chapter 8.

Debug Regristers

Core Services provides up to sixty-four (64) 64-bit debug registers. The number of registers is now selectable. For more information, see “Debug Registers” in Chapter 8.

Core Services also now provide the following:

SGI generated implementation scripts that support two synthesis tools: Synplify Pro and Xilinx XST, as described in “Synthesis Tool Specification” in Chapter 8.

A supplemental algorithm clock, as described in “Supplemental Algorithm Clock” in Chapter 8.

The new SGI RASC Algorithm Configuration tool described in Chapter 8, “SGI RASC Algorithm Configuration Tool” that enables you to configure memory, Streaming DMA, ADRs, and debug registers.

Added a second DMA engine in each direction for SRAMs, as described in “Core Services Architecture Overview” in Chapter 3.

Added information about the application algorithm secondary clock feature in “Supplemental Algorithm Clock” in Chapter 3.

Added information about a new RASCLIB_IGNORE_PARITY flag in Chapter 4, “RASC Abstraction Layer”.

Added descriptions for the rasclib_algorithm_malloc, rasclib_algorithm_mfree, rasclib_cop_malloc, and rasclib_cop_mfree functions in Chapter 4, “RASC Abstraction Layer”.

Added information about scaling applications with RASC in Chapter 6, “Scaling Applications with RASC”.

Added information about a new SGI RASC algorithm configuration tool in Chapter 8, “SGI RASC Algorithm Configuration Tool”.

More user control of Core Services local memory configurations

Addition of stream completion signalling mechanisms

Improved error correction/detection for local memories

Padding out incomplete cachelines from FPGA to host