Index
Prev
Index
Adding extractor directives to source code
Adding Extractor Directives to the Source Code
Algorithm Block
debug mode
Algorithm Run Modes
passing parameters
Passing Parameters to Algorithm Block
Algorithm Block modes
normal mode
Algorithm Run Modes
Algorithm control interface
Algorithm Control Interface
Algorithm debug mode
Implementation Options for Debug Mode
Algorithm design details
Algorithm Design Details
algorithm inputs and outputs
Input and Output Placement
Algorithm interfaces
Algorithm Interfaces
Algorithm run modes
Algorithm Run Modes
Algorithm streaming
algorithm iteration
Purpose
segment/segment size
Definitions
Algorithms, diagnostics , and commands
Running a Diagnostic
Basic algorithm control
Basic Algorithm Control
Bitstream development overview
Bitstream Development Overview
ccNUMA systems
Silicon Graphics ccNUMA Systems
Clock cycle based stepping
Clock Cycle Step Size Mode
Coding guidelines for timing
Recommended Coding Guidelines for Meeting Internal Timing Requirements
Core Services architecture overview
Core Services Architecture Overview
Core Services Block
Core Services Features
Core services, FPGA
FPGA Core Services
Designing an algorithm for multibuffering
Purpose
Determining FPGA run status
FPGA Run Status
Determining if an FPGA has run
Values and Stepping
Device driver
Device Driver
control and status registers
Control and Status Registers
Device driver API
Driver Application Programming Interface (API)
Device driver DMA
Input Direct Memory Access
Device driver example
Example Use of Device Driver
Device driver, function control
Function Control
Device driver, interrupts
Control and Status Registers
Device manager
RASC Device Manager
overview
RASC Device Manager Overview
structure
RASC Device Manager Structure
using
Using the Device Manager Command (
devmgr
)
Device manager load command
Device Manager Load FPGA Command
Driver API
Control and Status Registers
FPGA clock domains
FPGA Clock Domains
Algorithm Synthesis-time Parameters
FPGA core services
FPGA Core Services
FPGA design integration
RASC FPGA Design Integration
FPGA device values and stepping
Values and Stepping
FPGA programming
Overview of FPGA Programming
FPGA programming approach summary
SGI FPGA Programming Approach
FPGA registers
Registers
FPGA run status
FPGA Run Status
GDB commands
GDB Commands
GNU Debugger
connecting to internal signals
Connecting Internal Signals to the Debugger
GNU Debugger (GDB)
Using the GNU Project Debugger (GDB)
overview
Helpful SGI Tools
Hardware resets
Resets
Internal timing requirements
Recommended Coding Guidelines for Meeting Internal Timing Requirements
Loading the bitstream
Loading the Bitstream
Manually loading an FPGA
Device Manager Load FPGA Command
Memory distribution recommendations
Recommendations for Memory Distribution
Passing parameters to the algorithm block
Passing Parameters to Algorithm Block
RASC Abstraction Layer
Bitstream Development Overview
RASC Abstraction Layer Overview
functions
RASC Abstraction Layer Calls
how it works
How the RASC Abstraction Layer Works
RASC Algorithm Field Programmable Gate Array (FPGA) hardware
RASC Algorithm FPGA Hardware Design Guide
RASC Algorithm FPGA
implementation guide
RASC Algorithm FPGA Implementation Guide
RASC Algorithm FPGA implementation
flow
Summary of the Implementation Flow
Full-chip implementation
Full-chip Implementation
installation and setup
PC Installation
Makefile targets
Makefile Targets
Makefile.local customizations
Makefile.local Customizations
overview
Implementation Overview
pre-compiled cores
Implementation with Pre-synthesized Core
supported tools
Supported Tools and OS Versions
RASC hardware overview
RASC Hardware Overview
reconfigurable algorithm
RASC Hardware Overview
RASC overview
Silicon Graphics Reconfigurable Application-Specific Computing (RASC)
RASC Programming, getting started
Getting Started with RASC Programming
RASC software overview
RASC Software Overview
RASC tutorial
data flow algorithm
Data Flow Algorithm Tutorial
Streaming DMA Algorithm Tutorial
overview
Tutorial Overview
simple algorithm
Overview
system requirements
RASC Examples and Tutorials
Reconfigurable computing
An Overview of Reconfigurable Computing
Run status of an FPGA
FPGA Run Status
Running a diagnostic
Sample Test Bench Setup
Sample test bench constants and definitions
Sample Test Bench Constants and Dependencies
Sample test bench setup
Sample Test Bench Setup
Scalable System Port (SSP) Stub
Introduction to SSP Stub
compiling and running a test
Compiling and Running a Test
packet commands summary
Command Summary
sample testbench
Sample Test Bench
stub commands
SSP Stub Commands
verification environment
Verification Environment and Testbench
Simulating the design
Simulating the Design
SRAM
external memory read transaction control
External Memory Read Transaction Control
SRAM external memory write transaction control
External Memory Write Transaction Control
Streaming direct memory access (DMA)
Streaming Direct Memory Access
Streaming DMA
Streaming Direct Memory Access
Using the device manager
Using the Device Manager Command (
devmgr
)
Using the device manager command
Using the Device Manager Server (
devmgr_server
) Command
Using the GNU Project debugger
Using the GNU Project Debugger (GDB)
Variable step size mode
Clock Cycle Step Size Mode
Verilog, VHDL or header file
adding comments
Inserting Extractor Comments
VHDL and Verilog programming languages
Overview of FPGA Programming
Writing a diagnostic
Writing a Diagnostic