Table 2-1 provides a summary of the baseboard features.

Figure 2-1 shows a detailed view of the baseboard connectors and components.

A. Legacy Narrow SCSI

B. Legacy Wide SCSI

C. SMM Connector

D. IMB Connector

E. HDD Activity

F. HPIB Connector

G. ICMB Connector

H. Connector not Used

I. Lithium Battery

J. Memory Module Connector

K. Video Connector

L. USB, External Connector

M. Network Connector

N. Parallel Connector

O. COM1, COM2 Connector

P. Keyboard/Mouse

Q. Main Power 1

R. Auxiliary Power

S. Main Power 2

T. SMBus

U. Front Panel

V. IDE Connector

W. Floppy Connector

X. Configuration Jumpers

Y. Ultra 160 SCSI A

Z. Ultra 160 SCSI B

AA. Processor #1

BB. Processor #2

CC. Processor #3

DD. Processor #4

EE. Voltage Regulator Module (VRM) Connector #2

FF. Voltage Regulator Module (VRM) Connector #3

GG. Voltage Regulator Module (VRM) Connector #4

HH. 32-bit, 33 MHz Half-length PCI Slots

II. 64-bit, 66/33 MHz Hot-Plug PCI Slots

JJ. 64-bit, 33 MHz Hot-Plug PCI Slots

Each Intel Pentium III Xeon processor is packaged in a single edge contact (S.E.C.) cartridge. The cartridge includes the processor core with an integrated 32 KB primary (L1) cache, the secondary (L2) cache, a thermal plate, and a plastic cover.

The processor core and L2 cache components are on a pre-assembled printed circuit board, approximately 5 inches by 6 inches. The L2 cache and processor core L1 cache interface use a private bus isolated from the processor host bus. The L2 cache bus operates at the processor core frequency.

Each S.E.C. cartridge connects to the baseboard through a 330-pin SC330.1 compliant edge connector. A retention module attached to the baseboard secures the cartridge. Depending on configuration, the system supports one to four processors.

The processor external interface is multiprocessor (MP) ready and operates at 100 MHz. The processor contains a local Advanced Configuration and Power Interface (APIC) unit for interrupt handling in multiprocessor (MP) and uniprocessor (UP) environments.

The L2 cache is located on the substrate of the S.E.C. cartridge. The cache:

Main memory resides on an add-in board, called a memory module. The memory module contains slots for 16 DIMMs, each of which must be at least 64 MB, and is attached to the baseboard through a 330-pin connector, called the Memory Expansion Card Connector (MECC). The memory module supports PC-100 compliant registered ECC SDRAM memory modules. The ECC used for the memory module is capable of correcting single-bit errors (SBEs) and detecting 100 percent of double-bit errors over one code word. Nibble error detection is also provided.

System memory begins at address 0 and is continuous (flat addressing) up to the maximum amount of DRAM installed (exception: system memory is non contiguous in the ranges defined as memory holes using configuration registers). The system supports both base (conventional) and extended memory.

Memory amounts from 256 MB to 16 GB of DIMM are supported, with a 64/72-bit four-way-interleaved pathway to main memory, which is also located on the module. Therefore, data transfers between MADPs and DIMMs is in four-way interleave fashion. Each of the four DIMMs must be populated in a bank. The 16 slots are divided into four banks of four slots each. They are labeled A through D. Bank A contains DIMM sockets A1, A2, A3, and A4. Banks B, C, and D each contain 4 DIMM sockets and are named in the same fashion. There are silk screens on the module next to each DIMM socket to label its bank number. For the best thermal results, populate the banks from A to D. For example, populate bank A and then bank B. For best performance results, populate adjacent banks. For example, populate bank A and then bank C.

Figure 2-2 shows a detailed view of the memory module slots.

X. One of sixteen DIMM sockets

Y. One of four Memory Address Data Paths (MADPs)

Z. Memory Expansion Card Connector (MECC)

Each slot is identified by another notation. Sockets A1 through A4 are identified as J1 through J4 respectively. Sockets B1 through B4 are identified as J5 through J8. Sockets C1 through C4 are identified as J9 through J12. Sockets D1 through D4 are identified as J13 through J16.

Some operating systems and application programs use base memory while others use both conventional and extended memory. Examples are:

MS-DOS does not use extended memory; however, some MS-DOS utility programs like RAM disks, disk caches, print spoolers, and windowing environments use extended memory for better performance.

The BIOS automatically detects, sizes, and initializes the memory array, depending on the type, size, and speed of the installed DIMMs, and reports memory size and allocation to the system via configuration registers.

The baseboard has eight slots for PCI add-in boards supported by three PCI bus segments called PCI-A, PCI-B, and PCI-C. There are two slots on PCI-A, four slots on PCI-B, and two slots on PCI-C. PCI-C supports half-length boards (5.6 inches to 6.3 inches) only; the other slots support full-length boards.

The two slots for the PCI bus segment PCI-C consume a maximum of 375 mA of standby current on a 3.3 V Aux power line. The remaining six slots do not have any 3.3 V Aux capabilities.

Both PCI segments A and B allow you to add, remove, or replace PCI add-in boards installed in their slots without interrupting normal operation or powering down the system. To use this PCI Hot-Plug (PHP) feature, a server system requires PCI Hot-Plug software and PCI Hot-Plug capable add-in boards. PCI Hot-Plug software usually is a driver loaded for a specific operating system.

Each Hot-Plug PCI slot has two LEDs. The green LED indicates the state of power on for each slot. The amber LED indicates an error condition with that slot.

The table below summarizes typical LED states that you may encounter during a system's operation.

PCI features include:

The DesotoE2 Hot-Plug PCI controller is a 32-bit PCI bus agent that operates at either 33 or 66 MHz. The PCI controller manages PHP functionality for the PCI segment it resides on. There is a DesotoE2 controller on PCI segments A and B. The DesotoE2 PHP controller is:

The DesotoE2 is responsible for:

The Open South Bridge (OSB4) acts as a PCI-based fast IDE controller. The controller supports programmed I/O and bus master transfers. While the OSB4 supports two IDE channels, the baseboard uses only the primary IDE channel and provides a single 40-pin IDE connector.

The baseboard provides a dual external USB connector for the back panel of a server system. The connector is defined by the USB Specification, Revision 1.0. Both ports function identically with the same bandwidth.

The baseboard supports a 10BASE-T/100BASE-TX network subsystem based on the Intel 82559 Fast Ethernet Multifunction PCI/CARDBus controller. The Intel 82559 controller is a highly integrated PCI LAN controller in a 196-pin Ball Grid Array (BGA) supporting 10 or 100 Mbps fast Ethernet networks.

Supported network features include:

The baseboard provides an ATI Rage IIc VGA Graphics Accelerator, along with video Synchronous Graphics RAM (SGRAM) and support circuitry for an embedded Super VGA (SVGA) video subsystem. The ATI Rage IIc chip contains an SVGA video controller, clock generator, BitBLT engine, and a RAM digital-to-analog Converter (RAMDAC) in a 208-pin PQFP. One 256K x 32 SGRAM chip provides 2 MB of 10-ns video memory. The baseboard does not support adding video memory to the system. The SVGA subsystem supports a variety of modes, up to 1600 x 1200 resolution, or up to 16.7 M colors.

The SVGA subsystem also supports analog VGA monitors, single- and multi-frequency, interlaced and non-interlaced, up to 100 Hz vertical retrace frequency. The baseboard provides a standard 15-pin VGA connector and video blanking logic for server management console redirection support.

Depending on the environment, the controller displays up to 16.7 M colors in some video resolutions.

The baseboard includes two SCSI controllers. A dual function SCSI controller (Adaptec AIC-7899) is on the PCI-B bus, and a PCI wide SCSI controller (Adaptec AIC-7880) is on the PCI-C bus.

The Adaptec AIC-7899 SCSI controller contains two independent SCSI channels that share a single PCI bus master interface as a multifunction device, packaged in a 352-pin ball grid array (BGA). Internally, each channel is identical, capable of operations using either 16-bit Single-Ended (SE) or Low Voltage Differential (LVD) SCSI providing 40 MBps (Ultra-wide SE), 80 MBps (Ultra 2), or 160 MBps (Ultra 160).

Both channels attach to 68-pin 16-bit differential SCSI connector LVD interfaces. Each channel has its own set of PCI configuration registers and SCSI I/O registers. As a PCI bus master, the AIC-7899 controller supports burst data transfers on PCI up to the maximum rate of 266 MBps using on-chip buffers.

The Adaptec AIC-7880 controller contains a single SCSI channel with full-featured PCI bus master interface in a 160-pin Plastic Quad Flat Pack (PQFP). The controller supports either 8- or 16-bit Fast SCSI providing 10 MBps or 20 MBps (Fast-10) throughput, or Fast-20 SCSI that can burst data at 20 MBps or 40 MBps. As a PCI 2.1 bus master, the AIC-7880 controller supports burst data transfers on PCI up to the maximum rate of 133 MBps using the on-chip 256-byte FIFO.

The AIC-7880 implementation offers 8-bit or 16-bit SCSI connectors and operation at data transfer rates of 10, 20, or 40 MBps. The AIC-7880 controller also offers active negation outputs, controls for external differential transceivers, a disk activity output, and a SCSI terminator power-down control. Active negation outputs reduce the chance of data errors by actively driving both polarities of the SCSI bus, avoiding indeterminate voltage levels and common-mode noise on long cable runs. The SCSI output drivers can directly drive a 48-mA single-ended SCSI bus with no additional drivers. The SCSI segment can support up to 15 devices.

The AIC-7880 controller can be used as an 8-bit controller via the narrow, 50-pin connector and as a 16-bit controller via the wide, 68-pin connector. As a result, the AIC-7880 controller is not always at one end of the SCSI bus, and termination is controlled through some simple circuitry. The circuitry senses whether there is a device attached through the narrow 50-pin connector or the wide 68-pin connector. When there are devices attached to both connectors, the termination is on for the upper 8 bits of data and the parity bit associated with these data lines. All other signals are not terminated on board and are terminated by the devices attached through the connector. When there is a device attached to only one connector (either wide or narrow), all on-board termination is on.

IDE is a 16-bit interface for intelligent disk drives with AT disk controller electronics onboard. The Open South Bridge (OSB4) acts as a PCI-based fast IDE controller. The device controls:

The PS/2-compatible keyboard and mouse connectors are mounted in a single-stacked housing with the mouse connector over the keyboard. Externally, they appear as two connectors.

The user can plug in the keyboard and mouse to either connector before powering up the system. The BIOS detects these and configures the keyboard controller accordingly.

The keyboard controller is functionally compatible with the Intel 8042A micro controller. The system can be locked automatically if no keyboard or mouse activity occurs for a predefined length of time, if specified through the SSU. Once the inactivity (lockout) timer has expired, the keyboard and mouse do not respond until the previously stored password is entered.

Server management features are implemented using one micro controller called the Baseboard Management Controller (BMC).

The BMC and associated circuitry are powered from 5 V standby, which remains active when system power is switched off. The BMC is IPMI 1.0 compliant.

The primary function of the BMC is to autonomously monitor system platform management events and log their occurrence in the nonvolatile System Event Log (SEL). The BMC is compliant to the Intelligent Platform Management Interface Specification, Version 1.0. These events include over-temperature and over-voltage conditions, fan failure, or chassis intrusion. While monitoring, the BMC maintains the nonvolatile Sensor Data Record Repository (SDRR), from which run-time information can be retrieved. The BMC provides an interface to SDRR information, so software running on the server can poll and retrieve the current status of the platform. A shared register interface is defined for this purpose.

Field service personnel can retrieve SEL contents after system failure for analysis by using system management tools like Intel LANDesk Server Manager, Intel Server Control (ISC), or Direct Platform control (DPC). Because 5 V standby provides power the BMC, SEL (and SDRR) information is also available via the interperipheral management bus (IPMB). During monitoring, the BMC performs the following functions:

The SSU provides a number of security features to prevent unauthorized or accidental access to the system. Once the security measures are enabled, access to the system is allowed only after the user enters the correct password(s). For example, the SSU allows you to: