The Pentium III processor implements Dynamic Execution performance, a multi-transaction system bus, and Intel MMX media enhancement technology. Also, it offers Streaming SIMD (Single Instruction Multiple Data) extensions, which are 70 new instructions enabling advanced imaging, 3D, streaming audio and video, and speech recognition applications. The Pentium III processor delivers higher performance than the previous Pentium processor while maintaining binary compatibility with all previous Intel Architecture processors.

This system board supports 133-MHz GTL+ host bus frequencies for Pentium III processors running at 800 MHz and above.

The four DIMM sockets on board allow memory upgrade to a maximum of 2 GB using four 512-MB SDRAM (Synchronous DRAM) DIMMs. (The DIMM sockets also allow 1024 MB for a maximum upgrade of 4 GB in future models.) For data integrity, the default setting of the ECC (error-correcting code) function of the memory system in BIOS is enabled.

The system board supports 133-MHz registered SDRAM; 66-MHz SDRAM is not supported.

Figure 1-1 shows a block diagram of the SGI 1100 system board components.

This section describes the front controls and indicators of the SGI 1100 server, as shown in Figure 1-2.

Table 1-1 describes the front controls and indicators that are indicated in Figure 1-2.

The general event LED indicates the following occurrences:

If all of the preceding events recover, the Baseboard Management Controller (BMC) should turn off the LED.

This section describes the rear panel I/O ports and other features, as shown in Figure 1-3.

Table 1-2 describes the rear panel I/O ports and features that are indicated in Figure 1-3.

This section describes the location of the main components inside the SGI 1100 server, as shown in Figure 1-4.

Table 1-3 describes the internal components that are indicated in Figure 1-4.

The system supports the power-management function that conforms to the power-saving standards of the U.S. Environmental Protection Agency (EPA) Energy Star program. It also offers Plug-and-Play, which helps users avoid configuration problems and thus makes the system more user-friendly.

Table 1-4 lists the power-saving modes and their respective characteristics. These power management features are only available if the operating system running on the system supports them

IPMI is an open standard hardware manageability interface specification. It provides an architecture that defines how unique devices can all communicate with the CPU in a standard way.

With IPMI, the CPU only communicates one event to the IPMI event log. The CPU only “asks” what has changed since the last time it asked. Every device communicates directly, through IPMI, to the event log, which is used to record, in a consistent way, all status events for the unique device. This simplifies the agent-handling routine. The system only needs a single agent, and it does not need to be changed when you change from five devices to manage, for example, to six. And the system does not need to change the way the CPU checks the event log when a new device is added to the system; it always checks in the same way, whether there is one device or 100 devices. With IPMI, use of the CPU is minimized, so overall system performance improves.

The following are the four elements of IPMI, each of which is described in the sections that follow:

The system has the following major components: