The IRIS® HIPPI product is a network interface controller (hardware) and driver (software) providing data communication with the High–Performance Parallel Interface (HIPPI). The product provides HIPPI connectivity for CHALLENGE™ L and XL and Onyx™ platforms.
For networking, IRIS HIPPI supports TCP/IP over HIPPI-LE in conformance with RFC 1374 guidelines.
IRIS HIPPI provides an application programming interface (API) that customers can use to develop their own upper–layer applications (ULPs). Customer-developed ULPs can be designed to coexist with IRIS HIPPI's HIPPI-LE ULP module. See the IRIS HIPPI API Programmer's Guide (shipped with each IRIS HIPPI board) for details about developing upper–layer applications.
The IRIS HIPPI hardware must be installed by a Silicon Graphics system support engineer (SSE) or other person trained by Silicon Graphics in installation procedures. This document, IRIS HIPPI Installation Instructions, is provided to each SSE and contains complete details for hardware installation.
Installation and configuration of the software can be done by customers and/or SSEs. The IRIS HIPPI Administrator's Guide (shipped with each IRIS HIPPI board) provides software configuration details. The online IRIS HIPPI Release Notes provide software installation instructions.
The IRIS HIPPI network product adheres to the ANSI standards listed below, thus ensuring successful interoperability with other HIPPI equipment that is standards-compliant:
HIPPI-PH: X3.183-1991
HIPPI-SC: X3.222-1993
HIPPI-FP: X3.210-1992
HIPPI-LE: X3.218-1993
The IRIS HIPPI product includes an application programming interface (API) that allows customer-developed upper layer applications to control the IRIS HIPPI subsystem. The API is a character device interface. This interface is described in the IRIS HIPPI API Programmer's Guide that is shipped with each IRIS HIPPI board.
The IRIS HIPPI board has an AMD 29030 CPU that handles protocol processing and channel control. The board contains logic for handling transport layer (TCP and UDP) checksumming on both transmission and reception. These features provide two advantages: they increase the rate of data throughput for the board and free the host system's CPUs for work on user application tasks.