The IRIS® ATM-OC3c for CHALLENGE™ and Onyx™ product is a network interface controller (hardware) and driver (software) providing data communication over the Asynchronous Transfer Mode (ATM) network protocol with AAL5 at the data link layer and the Synchronous Optic Network (SONET) OC3c at the physical layer. The product provides one port of ATM/OC3c connectivity over multimode fiber optic cable for CHALLENGE and POWER CHALLENGE™ L and XL and Onyx and POWER Onyx™ platforms.
IRIS ATM provides an application programming interface (API) that customers can use to develop their own upper–layer applications. Customer-developed applications can be designed to coexist with the IRIS TCP/IP stack. See the IRIS ATM API Programmer's Guide for details about developing upper–layer applications.
The IRIS ATM hardware must be installed by a Silicon Graphics system support engineer (SSE) or other person trained by Silicon Graphics in installation procedures. This document, IRIS ATM-OC3c Board for CHALLENGE and Onyx Installation Instructions, is provided to each SSE and contains complete details for hardware installation.
Installation and configuration of the software can be done by customers and/or SSEs. The online IRIS ATM Release Notes provide software installation instructions. Configuration and verification instructions are provided in the online IRIS ATM Configuration Guide.
The IRIS ATM network product adheres to the ANSI and CCITT standards listed below, thus ensuring successful interoperability with other ATM/SONET equipment that is standards-compliant:
ATM: ATM User-Network Interface Specification, versions 3.0 and 3.1
SONET/SDH: B-ISDN User-Network Interface-Physical Interface Specification, CCITT Recommendation 1.432, June 1990.
The IRIS ATM product includes an application programming interface (API) that allows customer-developed upper layer applications to control the IRIS ATM subsystem. The API is a character device interface. This interface is described in the IRIS ATM API Programmer's Guide.
The IRIS ATM board has an AMD 29030 CPU that handles protocol processing and channel control. The board contains logic for handling transport layer (TCP and UDP) checksumming on both transmission and reception. These features provide two advantages: they increase the rate of data throughput for the board and free the host system's CPUs for work on user application tasks.