Chapter 4. Onyx2 DPLEX Theory of Operation

This chapter provides basic information on the operational theory of the Onyx2 InfiniteReality2 Digital Video Multiplexer Option (DPLEX). Any example configurations documented do not necessarily reflect what may be installed at a customer site.

The DG5-2/DPLEX assembly has also been associated with the code name DDO3. Note that DPLEX is not compatible with the DVP2 (also known as DDO2) option for Onyx2.

General Functions

The DPLEX option is primarily a frame rate delivery enhancement to the visual simulation capabilities of the Onyx2 product line. The DPLEX option supports genlocked cabling configurations where two or more graphics pipes run a single monitor (or other video output device) to obtain the highest graphics performance. By cascading the graphics outputs of two or more pipes, the DPLEX high-performance video multiplexer can provide buffered frames at the highest possible speeds.

Every cascaded DPLEX Onyx2 graphics pipe includes framebuffer space (located physically on the RM boards). This is where the graphics data is rendered before being sent through the digital-to-analog (DAC) conversion process. The framebuffer is divided into two parts: front buffer and back buffer. While the front buffer sends its rendered display data to the output DACs, the other (back buffer) fills with new image data. After the writing is complete, the buffers are “swapped,” which means that the front buffer becomes the back buffer and vice versa.

Digital and Video Functions

Although the DPLEX option shares some functionality with the DDO2 option product, the two are neither compatible nor complementary in function.

The DPLEX option provides:

  • digital video with 8-bit-per-component precision (8-bit DACs used for RGB analog outputs)

  • a multi-board signalling and control method allowing pipes to contribute video frames to a single display (or output) in a specific sequence

  • a 40-pin low-voltage differential signaling (LVDS) interconnect cabling scheme

  • video formats from 31 to 110 MHz in pixel clock frequency

  • a user-programmable video display frame sequence

  • a minimum of one frame of video from each DG5/DPLEX pipe (switching is done on frame boundaries)

  • the ability for each of the pipes in a cascaded DG5/DPLEX set to provide the cumulative video output (there is no hardware-designated video output master)

    Figure 4-1. DPLEX Data Flow Diagram

Connectivity Functions

Each system configuration has different connection requirements. This section lists the standard connections used with DPLEX options.


All DG5/DPLEX cascade assemblies are genlocked to a single video reference source:

  • The primary graphics pipe within the DPLEX cascade (pipe 0 in the examples shown in this guide).

  • An external genlocking signal (often called “house sync”).

In either case the genlock function uses 75 ohm coaxial cables and female BNC connectors. Each DG5 has a genlock in and a genlock loop through connector. The last genlock loop through connector in the daisy chain must always be terminated with a 75 ohm terminator.

Note: Genlocking of the DG5-2/DPLEX assemblies is accomplished specifically through the DG5 circuits.

Swap Ready

Each set of connected DG5/DPLEX boards must be interconnected with a swap ready cable. The cable uses BNC connectors to attach to the DG5 swap ready input.

Differential Signaling Cable (LVDS)

The low-voltage differential signaling (LVDS) cables always connect directly to the DPLEX daughter board. The LVDS video cables daisy-chain the DG5/DPLEX assemblies. Note that the graphics pipe (with the DG5/DPLEX) that is outputting the cascaded video information to a monitor or other device does not connect its 40-pin digital “video out” to another DG5/DPLEX assembly. There is no termination required with the LVDS cabling.