List of Tables

| Table of Contents | List of Figures | List of Examples | List of Tables |

Table 2-1. Signal Handling Interfaces
Table 3-1. schedctl() Real-Time Priority Range Remapping
Table 4-1. Frame Scheduler Operations
Table 4-2. Frame Scheduler schedctl() Support
Table 4-3. Signal Numbers Passed in frs_signal_info_t
Table 6-1. Multiprocessor Challenge VME Cages and Slots
Table 6-2. Power Channel-2 and VME bus Configurations
Table 6-3. VME Bus PIO Bandwidth
Table 6-4. VME Bus Bandwidth, VME Master Controlling DMA
Table 6-5. VME Bus Bandwidth, DMA Engine, D32 Transfer (Challenge/Onyx Systems)
Table 6-6. VME Bus Bandwidth, DMA Engine, D32 Transfer (Origin/Onyx 2 Systems)
Table A-1. Summary of Frame Scheduler Example Programs