Chapter 3. Processor View of I/O Space

I/O uncached space is divided into 256 equal segments of 4 GB each.

Each 4 GB I/O space is divided into seven 512 MB segments (BWin[7:1], a single 256 MB segment (LWin), and the remaining 256 MB aliases to LWin (see Chapter 2).

The LWin segment is further divided into sixteen 16 MB spaces, each directly mapped to one of the sixteen XIO devices, called widgets. The I/O space map, from the view of the SysAD bus on the processor, is given in Figure 3-1.

Figure 3-1. I/O Map (Per Node) as it Appears to the Processor

Figure 3-1 I/O Map (Per Node) as it Appears to the Processor

Little Window (LWin) Map

Big Windows (BWin) are set at 512 MB. LWin, however, is set at 256 MB and the remaining 256 MB region immediately above LWin aliases to LWin.

The LWin space contains sixteen 16 MB subspaces which map to the sixteen XIO devices or “widgets.” These sixteen subspaces are labelled Widget 0 through Widget F, and their base addresses are shown in Figure 3-1.

Widget 1 space is subdivided into two 8 MB spaces: Hub and IAlias, and these two 8 MB spaces are each subdivided into four 2 MB regions, mapping to the four Hub ASIC interfaces, as shown in Figure 3-1.

All of these spaces and subspaces are described below.

IAlias and Hub Spaces

The Hub's local registers reside within the IO uncached space, in Widget 1 portion of LWin space, as shown below in Figure 3-2.

Figure 3-2. Hub Local Register Space

Figure 3-2 Hub Local Register Space

When the NASID (the node ID) is not known — such as at boot time or during diagnostics — it is necessary to unambiguously access all the registers that are locally available to a node through a local R10000 processor.

To accommodate this access, the 16 MB Widget 1 space assigned to the Hub is further divided into a pair of 8 MB regions, IAlias and Hub, as shown in Figure 3-2.

  • Accesses to the lower 8 MB region labelled IAlias are not checked for a NASID. A processor cannot directly address a remote IAlias space, which means the IAlias space is reserved for the use of processors local to it. IAlias space is used to avoid having to load a NASID when running code such as an interrupt handler and communicating with local registers.

  • Accesses to the upper 8 MB region labelled Hub are checked for a match with the correct NASID. If there is a match, these accesses map to the IAlias space. Since the NASID is checked, remote accesses to the Hub space are permissible.

Each 8 MB space is further divided into regions corresponding to the Hub interfaces, as described in the next section.

Hub Local Register Regions

The Hub chip has four major interfaces:

  • the IO interface (II)

  • the CrayLink Interconnect (NI)

  • the memory/directory interface (MD)

  • the processor interface (PI)

Each 8 MB IAlias and Hub subspace is further divided into four 2 MB regions, as shown in Figure 3-1 and Figure 3-2. These four 2 MB regions represent local register spaces for the four interfaces of the Hub (NI, PI, MD, II), shown in Figure 3-3. There are a small number of Hub crossbar registers, and these reside in the MD region. The next section describes the conditions that must be met for accessing these local register regions.

Figure 3-3. Hub Chip Interfaces

Figure 3-3 Hub Chip Interfaces

Accessing the Hub Local Registers

In accessing the Hub's local registers, four separate conditions must be met before a target (NI, PI, MD, II) can recognize a valid address:

  1. The access must be to LWin; that is, A[31:28], must be zero.

  2. A[27:24] must be equal to 0001 (indicating Widget 1 space in LWin).

  3. If A[23] is set (indicating an access to Hub space), the Source[10:2] field of the incoming request must match this node's NASID. If A[23] is clear, Source[10:2] is ignored, allowing access to the IAlias space.

  4. A[22:0] is decoded to determine which 2 MB local register space is being addressed (CrayLink Interconnect, I/O, memory, or processor).

SysAD[2:0] are converted to byte-enable bits to allow Little and Big Endian accesses that are not doubleword aligned.

Figure 3-4 shows LWin address mapping in M Mode.

Figure 3-4. Accessing the Hub Local Registers in LWin Space

Figure 3-4 Accessing the Hub Local Registers in LWin Space

The kernel transparently converts the Hub and XIO addresses, and handles Node register accesses.

Big Window (BWin[7:1]) Map

The remaining seven big windows can be mapped to any region within the XIO address space through a translation table. There are always only seven big windows available per node. In M Mode, up to 4 GB of addressable space is allotted to each node, so each BWin is 512 MB.

In the present implementation of Origin2000, Widget 1 space hosts the Hub registers and currently only widgets 0, and 8 through F are addressable in the Crossbow. Their addresses are shown in Figure 3-1.

XIO uses a 48-bit address. When converting a 40-bit SysAD bus address to XIO format, only 5 of the offset bits are programmable. In M Mode a 16 GB address per widget is provided to the processor. This space is sufficient for the current range of devices; the 512 MB big window can be located anywhere within the 16 GB window available per widget.

Figure 3-5 shows the address mapping of the big windows space, BWin. M Mode addressing capability per widget is 16 GB, A[33:0].

Figure 3-5. BWin Space Access in M Mode

Figure 3-5 BWin Space Access in M Mode