Index
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Index
address space
functions that change
Isolating a CPU From TLB Interrupts
of VME bus devices
VME Address Space Mapping
affinity scheduling
Understanding Affinity Scheduling
affinity value
Understanding Affinity Scheduling
aio_cancel()
Scheduling Asynchronous I/O
aio_error()
Checking for Completion
Polling for Status
example code
Asynchronous I/O Example
aio_fsync()
Assuring Data Integrity
aio_read()
Scheduling Asynchronous I/O
example code
Asynchronous I/O Example
from callback
Establishing a Callback Function
implies aio_init()
Implicit Initialization
aio_return()
Checking for Completion
example code
Asynchronous I/O Example
aio_sgi_init()
Initializing with aio_sgi_init()
example code
Asynchronous I/O Example
aio_suspend()
Checking for Completion
example code
Asynchronous I/O Example
aio_write()
Scheduling Asynchronous I/O
example code
Asynchronous I/O Example
from callback
Establishing a Callback Function
implies aio_init()
Implicit Initialization
aircraft simulator
Aircraft Simulators
asynchronous I/O
Asynchronous I/O
aiocb structure
Checking for Completion
Asynchronous I/O Control Block
difference between 5.3 and 5.2
Two Implementation Versions
example code
Asynchronous I/O Example
in IRIX 6.0
Two Implementation Versions
initializing
Initializing Asynchronous I/O
multiple operations to one file
Multiple Operations to One File
not compatible with guaranteed rate
Sharing Access to Guaranteed Files
notification methods
Checking for Completion
POSIX 1003.1b-1993
Two Implementation Versions
request priority no longer supported
Asynchronous I/O Control Block
signal use
Checking for Completion
average data rate
Requirements on Data Collection Systems
barrier()
example code
Asynchronous I/O Example
brk()
modifies address space
Isolating a CPU From TLB Interrupts
cache
affinity scheduling
Understanding Affinity Scheduling
warming up in first frame
Process Execution
cacheflush()
Isolating a CPU From TLB Interrupts
CD-ROM audio library
CD-ROM and DAT Audio Libraries
CPU
assign interrupt to
Assigning Interrupts to CPUs
assign process to
Assigning Work to a Restricted CPU
CPU 0 not used by Frame Scheduler
Frame Scheduler Basics
isolating from sprayed interrupts
Isolating a CPU From Sprayed Interrupts
isolating from TLB interrupts
Isolating a CPU From TLB Interrupts
making nonpreemptive
Making a CPU Nonpreemptive
restricting to assigned processes
Mapping Processes and CPUs
Restricting a CPU From Scheduled Work
cycle counter
Hardware Cycle Counter
as Frame Scheduler time base
High-Resolution Timer
drift rate of
Hardware Cycle Counter
precision of
Hardware Cycle Counter
DAT audio library
CD-ROM and DAT Audio Libraries
data collection system
Major Types of Real-Time Programs
Data Collection Systems
average data rate
Requirements on Data Collection Systems
peak data rate
Requirements on Data Collection Systems
requirements on
Requirements on Data Collection Systems
/dev/ei
External Interrupts
device
opening
How Devices Are Used
device driver
as Frame Scheduler time base
The Frame Scheduler Device Driver Interface
entry points to
Device Driver Entry Points
for VME bus master
DMA Access to Master Devices
generic SCSI
Generic SCSI Device Driver
in synchronous input
Synchronous Input
reference pages
Device Driver Entry Points
tape
System Tape Device Driver
device service time
Components of Interrupt Response Time
Device Service Time
not guaranteed
Service Time for Other Devices
direct disk output
Using Direct I/O
disk output
synchronous direct
Using Direct I/O
synchronous unbuffered
Using Synchronous Writing
dispatch cycle time
Dispatch Cycle
Components of Interrupt Response Time
dlopen()
Isolating a CPU From TLB Interrupts
DMA engine for VME bus
DMA Engine Access to Slave Devices
performance
DMA Engine Access to Slave Devices
DMA mapping
DMA Mapping
DMA to VME bus master devices
DMA Access to Master Devices
dslib
Generic SCSI Device Driver
DSO
Isolating a CPU From TLB Interrupts
dynamic shared object. See DSO
Isolating a CPU From TLB Interrupts
/etc/autoconfig command
Assigning Interrupts to CPUs
external interrupt
External Interrupts
External Interrupts
with Frame Scheduler
External Interrupts
fcntl()
example code
Creating a Real-time File
file descriptor
of a device
How Devices Are Used
with asynchronous I/O
Asynchronous I/O Control Block
with guaranteed-rate I/O
Requesting a Guarantee
fork()
rate guarantee not inherited
Sharing Access to Guaranteed Files
frame interval
Frame Rate
frame rate
Frame Rate
of plant control simulator
Plant Control Simulators
of virtual reality simulator
Virtual Reality Simulators
Frame Scheduler
Using the Frame Scheduler
REACT/Pro Frame Scheduler
advantages
Advantages of the Frame Scheduler
and cycle counter
High-Resolution Timer
and external interrupt
External Interrupts
and R4000 timer
On-Chip Timer Interrupt
and vertical sync
Vertical Sync Interrupt
background discipline
Background Discipline
continuable discipline
Continuable Discipline
CPU 0 not used by
Frame Scheduler Basics
definition of frame
How Frames Are Defined
design process
Designing With the Frame Scheduler
device driver initialization
Frame Scheduler Initialization Function
device driver interface
The Frame Scheduler Device Driver Interface
device driver interrupt
Generating Interrupts
device driver termination
Frame Scheduler Termination Function
device driver use
Device Driver Overview
example code
Frame Scheduler Examples
exception handling
Handling Frame Scheduler Exceptions
FRS control process
The FRS Control Process
Using Multiple Synchronized Schedulers
frs_run flag
Scheduler Flags frs_run and frs_yield
frs_yield flag
Scheduler Flags frs_run and frs_yield
interface to
The Frame Scheduler API
interval timers not used with
Using Timers with the Frame Scheduler
major frame
Frame Scheduling
minor frame
Frame Scheduling
multiple synchronized
Using Multiple Synchronized Schedulers
overrun exception
Realtime Discipline
Exception Types
overrunnable discipline
Overrunnable Discipline
pausing
Pausing Frame Schedulers
process outline for multiple
Implementing Synchronized Schedulers
process outline for single
Implementing a Single Frame Scheduler
process structure
Process Execution
realtime discipline
Realtime Discipline
scheduling disciplines
Using the Scheduling Disciplines
scheduling rules of
Scheduling Within a Minor Frame
signals produced by
Setting Frame Scheduler Signals
Handling Signals in the FRS Controller
software interrupt to
Software Interrupt
starting up
Starting Multiple Schedulers
time base selection
Selecting a Time Base
How Frames Are Defined
underrun exception
Exception Types
Realtime Discipline
underrunable discipline
Underrunable Discipline
using consecutive minor frames
Using Multiple Consecutive Minor Frames
warming up cache
Process Execution
FRS control process
The FRS Control Process
Using Multiple Synchronized Schedulers
design of
Implementing a Single Frame Scheduler
receives signals
Setting Frame Scheduler Signals
frs_create_master()
Synchronized Schedulers: the Sync-Master Process
Registering the Initialization and Termination Functions
Implementing a Single Frame Scheduler
frs_create_slave()
Synchronized Schedulers: Sync-Slave Processes
frs_destroy()
Synchronized Schedulers: the Sync-Master Process
Synchronized Schedulers: Sync-Slave Processes
Implementing a Single Frame Scheduler
frs_driver_export()
Registering the Initialization and Termination Functions
frs_enqueue()
Synchronized Schedulers: Sync-Slave Processes
Synchronized Schedulers: the Sync-Master Process
Scheduling Within a Minor Frame
Using the Scheduling Disciplines
Implementing a Single Frame Scheduler
frs_handle_driverintr()
Generating Interrupts
frs_join()
Synchronized Schedulers: the Sync-Master Process
Starting Multiple Schedulers
Implementing a Single Frame Scheduler
Synchronized Schedulers: Sync-Slave Processes
Process Execution
frs_resume()
Pausing Frame Schedulers
frs_setattr()
example code
Setting Exception Policies
Setting Exception Policies
frs_start()
Starting Multiple Schedulers
Synchronized Schedulers: the Sync-Master Process
Implementing a Single Frame Scheduler
Synchronized Schedulers: Sync-Slave Processes
frs_stop()
Pausing Frame Schedulers
frs_userinter()
Software Interrupt
frs_yield
Process Execution
frs_yield()
with overrunable discipline
Overrunnable Discipline
fsync()
Synchronous Output
Using Synchronous Writing
gang scheduling
Gang Scheduling
Using Gang Scheduling
GRIO. See guaranteed-rate I/O
Guaranteed-Rate I/O
grio_remove_request()
Releasing a Guarantee
grio_request()
Requesting a Guarantee
example code
Guaranteed-Rate Request
ground vehicle simulator
Ground Vehicle Simulators
guaranteed-rate I/O
Guaranteed-Rate I/O
creating a real-time file
Creating a Real-time File
example code
Guaranteed-Rate Request
hard guarantee
Hard Guarantees
requesting a guarantee
Requesting a Guarantee
requires XFS
Guaranteed-Rate I/O Basics
requires XLV volume
Guaranteed-Rate I/O Basics
soft guarantee
Soft Guarantees
tied to PD and I-node
Sharing Access to Guaranteed Files
video on demand guarantee
Video On Demand (VOD) Guarantees
hardware latency
Components of Interrupt Response Time
Hardware Latency
hardware simulator
Hardware-in-the-loop (HITL) Simulators
input
synchronous
Synchronous Input
interchassis communication
Interchassis Communication
interprocess communication
Interprocess Communication
interrupt
assign to CPU
Assigning Interrupts to CPUs
controlling distribution of
Controlling Interrupt Distribution
external. See external interrupt
External Interrupts
group. See interrupt group
Selecting a Time Base
isolating CPU from
Isolating a CPU From Sprayed Interrupts
propogation delay
Hardware Latency
response time. See interrupt response time
Minimizing Interrupt Response Time
spraying
Isolating a CPU From Sprayed Interrupts
TLB
Isolating a CPU From TLB Interrupts
vertical sync
Vertical Sync Interrupt
Understanding the Vertical Sync Interrupt
interrupt group
Selecting a Time Base
Frame Scheduler passes to device driver
Frame Scheduler Initialization Function
not used with cycle counter
High-Resolution Timer
to distribute external interrupt
External Interrupts
to distribute vertical sync
Vertical Sync Interrupt
interrupt response time
Minimizing Interrupt Response Time
200 microsecond guarantee
Maximum Response Time Guarantee
components
Components of Interrupt Response Time
device service not guaranteed
Service Time for Other Devices
device service time
Device Service Time
dispatch cycle
Dispatch Cycle
hardware latency
Hardware Latency
kernel service not guaranteed
Kernel Critical Sections
restrictions on processes
Kernel Critical Sections
software latency
Software Latency
interrupts
unavoidable from timer
Unavoidable Timer Interrupts
interval timer
not used with Frame Scheduler
Using Timers with the Frame Scheduler
ioctl()
and device driver
Device Driver Entry Points
IPL statement
Assigning Interrupts to CPUs
IRIS InSight
About This Guide
irix.sm configuration file
Assigning Interrupts to CPUs
kernel
affinity scheduling
Understanding Affinity Scheduling
critical section
Kernel Critical Sections
gang scheduling
Using Gang Scheduling
interrupt response time
Software Latency
originates signals
Signals
priority assignment
Priorities
real-time features
Kernel Facilities for Real-Time Programs
scheduling
Scheduling Concepts
tick
Tick Interrupts
time slice
Tick Interrupts
latency
hardware
Hardware Latency
Components of Interrupt Response Time
software
Components of Interrupt Response Time
Software Latency
lio_listio()
Scheduling Asynchronous I/O
lock
Locks
defined
Locks
effect of gang scheduling
Using Gang Scheduling
set by spinning
Locks
locking virtual memory
Locking Virtual Memory
lseek()
with asynchronous I/O
Asynchronous I/O Control Block
with guaranteed-rate I/O
Video On Demand (VOD) Guarantees
major frame
Frame Scheduling
MAP_AUTOGROW flag
Isolating a CPU From TLB Interrupts
MAP_LOCAL flag
Isolating a CPU From TLB Interrupts
memory
shared. See shared memory
Shared Memory Segments
memory mapping
for I/O
Memory-Mapped I/O
minor frame
Frame Scheduling
Scheduling Within a Minor Frame
mmap()
Isolating a CPU From TLB Interrupts
mpadmin command
assign clock processor
Assigning the Clock Processor
make CPU nonpreemptive
Making a CPU Nonpreemptive
restrict CPU
Restricting a CPU From Scheduled Work
unrestrict CPU
Restricting a CPU From Scheduled Work
mprotect()
Isolating a CPU From TLB Interrupts
multiprocessor architecture
affinity scheduling
Understanding Affinity Scheduling
and Frame Scheduler
Using Multiple Synchronized Schedulers
munmap()
Isolating a CPU From TLB Interrupts
mutual exclusion primitive
Mutual Exclusion Primitives
NOINTR statement
Isolating a CPU From Sprayed Interrupts
open()
example code
Creating a Real-time File
of a device
How Devices Are Used
operator
affected by transport delay
Transport Delay
in virtual reality simulator
Virtual Reality Simulators
of simulator
Simulators
output
synchronous
Synchronous Output
to disk is buffered
Using Synchronous Writing
overrun in data collection system
Requirements on Data Collection Systems
overrun in Frame Scheduler
Realtime Discipline
page fault
causes TLB interrupt
Isolating a CPU From TLB Interrupts
prevent by locking memory
Locking Virtual Memory
peak data rate
Requirements on Data Collection Systems
PIO access to VME devices
PIO Access
PIO address mapping
PIO Address Space Mapping
plant control simulator
Plant Control Simulators
power plant simulator
Plant Control Simulators
priority
Priorities
process
assign to CPU
Assigning Work to a Restricted CPU
FRS control
The FRS Control Process
mapping to CPU
Mapping Processes and CPUs
priority of
Priorities
time slice
Time Slices
process control
Major Types of Real-Time Programs
process group
Gang Scheduling
and gang scheduling
Using Gang Scheduling
process id
identifies rate guarantee
Sharing Access to Guaranteed Files
propogation delay. See hardware latency
Hardware Latency
pset command
and restricted CPU
Restricting a CPU From Scheduled Work
R4000 timer
On-Chip Timer Interrupt
REACT
About This Guide
REACT/Pro
About This Guide
read()
and device driver
Device Driver Entry Points
synchronous
Synchronous Input
with guaranteed-rate I/O
Requesting a Guarantee
real-time program
and Frame Scheduler
REACT/Pro Frame Scheduler
data collection
Data Collection Systems
Major Types of Real-Time Programs
defined
Defining Real-Time Programs
disk I/O by
Optimizing Disk I/O for a Real-Time Program
frame rate
Requirements on Simulators
process control
Major Types of Real-Time Programs
simulator
Major Types of Real-Time Programs
Simulators
types of
Real-Time Programs
reflective shared memory
Reflective Shared Memory
response time. See interrupt response time
Minimizing Interrupt Response Time
restricting a CPU
Restricting a CPU From Scheduled Work
runon command
Assigning Work to a Restricted CPU
schedctl()
Using Gang Scheduling
Assigning Work to a Restricted CPU
example code
Using Gang Scheduling
with Frame Scheduler
System Call Interface for Fortran and Ada
scheduling
Scheduling Concepts
affinity type
Understanding Affinity Scheduling
gang type
Gang Scheduling
Using Gang Scheduling
scheduling discipline: See also Frame Scheduler scheduling disciplines
Using the Scheduling Disciplines
SCSI interface
SCSI Devices
generic device driver
Generic SCSI Device Driver
semaphore
Semaphores
defined
Semaphores
sginap()
Locks
example code
Asynchronous I/O Example
shared memory
Shared Memory Segments
reflective
Reflective Shared Memory
shmctl()
Isolating a CPU From TLB Interrupts
shmget()
Isolating a CPU From TLB Interrupts
sigaction()
example code
Asynchronous I/O Example
with asynchronous I/O
Establishing a Completion Signal
sigevent structure
Asynchronous I/O Control Block
signal
Signals
delivery priority
Signal Families
generated in asynchronous I/O
Checking for Completion
latency
Signal Delivery and Latency
signal numbers
Signal Families
SIGUSR1
Setting Frame Scheduler Signals
SIGUSR2
Setting Frame Scheduler Signals
with Frame Scheduler
Using Signals Under the Frame Scheduler
signal handler
when setting up Frame Scheduler
Synchronized Schedulers: Sync-Slave Processes
Implementing a Single Frame Scheduler
Synchronized Schedulers: the Sync-Master Process
SIGRTMIN on dequeue
Setting Frame Scheduler Signals
sigsuspend()
Checking for Completion
SIGUSR1
on underrun
Setting Frame Scheduler Signals
SIGUSR2
on overrun
Setting Frame Scheduler Signals
sigwait()
Checking for Completion
simulator
Simulators
Major Types of Real-Time Programs
aircraft
Aircraft Simulators
control inputs to
Simulators
Plant Control Simulators
frame rate of
Plant Control Simulators
Requirements on Simulators
ground vehicle
Ground Vehicle Simulators
hardware
Hardware-in-the-loop (HITL) Simulators
operator of
Simulators
plant control
Plant Control Simulators
state display
Simulators
virtual reality
Virtual Reality Simulators
world model in
Simulators
sockets
Socket Programming
software latency
Components of Interrupt Response Time
Software Latency
spin lock
Locks
sproc()
CPU assignment inherited
Assigning Work to a Restricted CPU
modifies address space
Isolating a CPU From TLB Interrupts
rate guarantee not inherited
Sharing Access to Guaranteed Files
sprocsp()
Isolating a CPU From TLB Interrupts
example code
Asynchronous I/O Example
striped volume
Video On Demand (VOD) Guarantees
synchronous disk output
Using Synchronous Writing
sys/param.h
Tick Interrupts
sysmp()
Assigning Work to a Restricted CPU
assign process to CPU
Assigning Work to a Restricted CPU
example code
Making a CPU Nonpreemptive
Restricting a CPU From Scheduled Work
Restricting a CPU From Scheduled Work
Assigning Work to a Restricted CPU
Assigning the Clock Processor
isolate TLB interrupts
Isolating a CPU From TLB Interrupts
make CPU nonpreemptive
Making a CPU Nonpreemptive
number of CPUs
Restricting a CPU From Scheduled Work
restrict CPU
Restricting a CPU From Scheduled Work
Restricting a CPU From Scheduled Work
run process on any CPU
Assigning Work to a Restricted CPU
syssgi
set flush interval
Using a Delayed System Buffer Flush
tape device
System Tape Device Driver
telemetry
Major Types of Real-Time Programs
test_and_set
Mutual Exclusion Primitives
tick
Tick Interrupts
disabling
Making a CPU Nonpreemptive
time base for Frame Scheduler
Selecting a Time Base
time slice
Tick Interrupts
timer interrupts unavoidable
Unavoidable Timer Interrupts
TLB update interrupt
Isolating a CPU From TLB Interrupts
transport delay
Transport Delay
udmalib
DMA Engine Access to Slave Devices
underrun, in Frame Scheduler
Realtime Discipline
uspsema()
example code
Asynchronous I/O Example
usvsema()
example code
Asynchronous I/O Example
vertical sync interrupt
Vertical Sync Interrupt
Understanding the Vertical Sync Interrupt
video on demand (VOD). See guaranteed-rate I/O, video on demand
Video On Demand (VOD) Guarantees
virtual memory
locking
Locking Virtual Memory
virtual reality simulator
Virtual Reality Simulators
VME bus
The VME Bus
address space mapping
VME Address Space Mapping
assign interrupt to CPU
Assigning Interrupts to CPUs
configuration
VME Bus Attachments
DMA mapping
DMA Mapping
DMA to master devices
DMA Access to Master Devices
performance
PIO Access
DMA Engine Access to Slave Devices
DMA Access to Master Devices
PIO access
PIO Access
PIO address mapping
PIO Address Space Mapping
udmalib
DMA Engine Access to Slave Devices
write()
and device driver
Device Driver Entry Points
direct
Using Direct I/O
synchronous
Synchronous Output
Using Synchronous Writing
with guaranteed-rate I/O
Creating a Real-time File
Requesting a Guarantee