Appendix E. VMEbus Implementation
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Appendix E. VMEbus Implementation

This appendix provides information to help users select third-party VME boards for the Challenge system.

The reader may also wish to consult related books such as the following for additional background:

Warning: All board installations or removals should be performed only by personnel certified by Silicon Graphics. Unauthorized access to the card cage area could result in system damage, or possible bodily harm, and could void the warranty for the system.

General Information

The VME interface in the Challenge system supports all protocols defined in Revision C of the VME specification, plus the A64 and D64 modes defined in Revision D. For the acceptable VME address ranges, read the /var/sysgen/system file.

Note: The Challenge system does not support VSBbus mode.

VME Board Dimensions

The Challenge board slots have a 9U (vertical) form factor and measure 15.75 inches (400 mm) horizontally. The board edges must also be less than or equal to 0.062 inches (1.57 mm). If the board is thicker, the edge of the board must be milled to fit into the card guide. In addition. the center-to-center board spacing is 0.8 inch (20.3 mm).

Rackmount VME Issues

This section discusses specific VME issues for the Challenge XL rackmount system.

Card Cage 1 and 2 VME Issues

There are no VME slots in the card cage 1 in either the Challenge system. See Table E-1 for the available number of VME slots in card cage 2.

Table E-1. VME Slot Availability in Card Cage 2

System

Card Cage 2 VME Slots

Challenge XL

5

Both systems also supply approximately 40 watts of 5 V power per VME slot (nominally). The card cage 2 also receives approximately 200 to 250 linear feet per minute (LFM) of air flow.

Card Cage 3 VMEbus Issues

The card cage 3 (CC3), which is optional on the Challenge XL rackmount system, supplies additional VME slots. The CC3 in a Challenge system has 19 slots. The CC3 provides approximately 70 W of 5 V power per VME slot. This assumes the presence of three 505 power boards and one 512 power board. The card cage 3 also receives approximately 200 to 250 LFM of air flow through the chassis.

Exceeding the Normal VME Power Rating Per Slot

If a VME board requires more than the normal slot power allotment (approximately 40 watts of 5 V power per slot in CC2 or greater than 70 watts in a card cage 3), the board still can be used. However, the user needs to ensure that the board has the proper air flow (for cooling purposes) and sufficient available power.

To help maintain proper cooling (according to manufacturer's specifications), the board may need special custom baffles or a set of non-component, enclosure boards to surround the VME board with sufficient air flow.

Note: These custom air flow devices will need to be supplied by the customer.

In addition, a third-party VME board that requires more than the normal VME slot power can be used, as long the following conditions are met.

  • The board does not draw more than the amount of power for allocated for VME board use.

  • The board does not exceed the power rating for the VME pins.

  • The board uses all three "P" connectors on the system backplane, the P1, P2, and P3. See Table E-2 through Table E-4) for pinout information.

If these guidelines are followed, a single VME board can draw as much as 150 watts of 5 V power.

In the CC2, you can install two 75-watt VME boards (providing the boards were sufficiently cooled). However, as a result, you could not install any additional VME boards, since the VME power allotment would already be saturated. It is also possible to use a single 150-watt VMEbus board in the CC2, providing the remaining VME slots are also not used.

In the CC3, you can install up to 9 150-watt boards, assuming that all potential power boards (three 505 and one 512) are installed. However, as a result, the remaining VME slots cannot then be used.

Special VME Considerations

Generally, there are VME boards or devices that should not be integrated into the Challenge system. This section provides guidelines for selecting or designing third-party VME board.

Caution: Be sure to observe these general rules to avoid possible damage to the VMEbus and system.

  • Devices acting as an A16 VME MASTER can not access system memory via DMA.

  • Devices should require 8-bit interrupt vectors only.

  • Devices must not require UAT (unaligned transfers or tri-byte) access from the Challenge system.

  • Devices in Slave mode must not require address modifiers, other than Supervisory/Nonprivileged data access.

  • While in VME Master mode, devices must only access the system memory using Nonprivileged data access or Nonprivileged block transfers.

  • Devices must have the ability to be configured so that their address range does not conflict with those used by the Challenge system. The device should also be able to respond to addresses generated by the system.

  • The Challenge system does not support VSBbus boards.

  • Be sure to place boards starting in the first VME slot, or jumper the daisy-chained signals across the empty slots. Otherwise, this will break the interrupt acknowledge and bus arbitration schemes.

  • Metal face plates or front panels on VME boards may need to be removed. The plate could prevent the I/O door from properly closing and possibly damage I/O bulkhead.

    Note: In some VME enclosures, these plates supply the required additional EMI shielding. However, the Challenge chassis already provides sufficient shielding for boards inside the chassis, so these plates are not necessary.

VME Pins

Table E-2 through Table E-4 list the pin assignments of the VME P1, P2, and P3 connectors. Table E-5 describes the pin signals.

Note: No connections are made to rows A and C of connector P2. These lines are not bussed across the backplane. The P3 connector uses the Sun power convention. In addition, the Challenge system does not generate ACFAIL* or SYSFAIL*. The SERCLK and SERDAT* are also unused.

The Challenge system supplies the defined voltages to the bus, also asserts SYSREST*, and drives SYSCLK (SYSCLK is driven at 16 MHz).

On the Challenge backplanes, the unused VME pins are no connects on the first four VME slots, but on the fifth, these pins are connected to the VCAM.

Caution: In addition, the Challenge system does not support VSBbus boards.

Table E-2. P1 VME Pin Assignments

Pin

Row A

Row B

Row C

1

D00

BBSY*

D08

2

D01

BCLR*

D09

3

D02

ACFAIL

D10

4

D03

BG01N*

D11

5

D04

BG0OUT*

D12

6

D05

BG1IN*

D13

7

D06

BG1OUT*

D14

8

D07

BG2IN*

D15

9

GND

BG2OUT*

GND

10

SYSCLK

BG3IN*

SYSFAIL*

11

GND

BG3OUT*

BERR*

12

DS1

BR0*

SYSRESET*

13

DS0

BR1

LWORD*

14

WRITE*

BR2*

AM5

15

GND

BR3*

A23

16

DTACK*

AM0

A22

17

GND

AM1

A21

18

AS*

AM2

A20

19

GND

AM3

A19

20

IACK*

GND

A18

21

IACKIN*

SERCLK

A17

22

IACKOUT*

SERDAT*

A16

23

AM4

GND

A15

24

A07

IRQ7*

A14

25

A06

IRQ6*

A13

26

A05

IRQ5*

A12

27

A04

IRQ4*

A11

28

A03

IRQ3*

A10

29

A02

IRQ2*

A09

30

A01

IRQ1*

A08

31

-12V

+5VSTDBY

+12V

32

+5V

+5V

+5V


Table E-3. P2 VME Pin Assignments

Pin

Row A (Note: This row is user-defined.)

Row B

Row C (Note: This row is user-defined).

1

 

+5V

 

2

 

GND

 

3

 

RESERVED

 

4

 

A24

 

5

 

A25

 

6

 

A26

 

7

 

A27

 

8

 

A28

 

9

 

A29

 

10

 

A30

 

11

 

A31

 

12

 

GND

 

13

 

+5V

 

14

 

D16

 

15

 

D17

 

16

 

D18

 

17

 

D19

 

18

 

D20

 

19

 

D21

 

20

 

D22

 

21

 

D23

 

22

 

GND

 

23

 

D24

 

24

 

D25

 

25

 

D26

 

26

 

D27

 

27

 

D28

 

28

 

D29

 

29

 

D30

 

30

 

D31

 

31

 

GND

 

32

 

+5V

 


Table E-4. P3 VME Pin Assignments

Pin

Row A

Row B

Row C

1 through 25

+5V

Not connected

GND

26, 27

+12V

Not connected

+12V

28, 29

-12V

Not connected

-12V

30 through 32

-5V

Not connected

-5V


Note: In some Challenge VME backplanes, P3B is used for Silicon Graphics purposes.

Table E-5. Signal Definitions

Signal Name

Definition

D00 through D31

Data lines. These lines are tri-stated and are not defined until the data strobes (DS0* and DS1*) are asserted by the MASTER.

A00 through A31

Address lines. These lines are tri-stated and are not defined until the address strobe (AS*) is asserted by the MASTER.

AM0 through AM5

Address modifier lines. Asserted by the MASTER and indicate the type of data transfer to take place. VME SLAVEs look at the lines to determine if they will respond and what type of response to make.

DS0, DS1

Data Strobe lines. Asserted by the MASTER and indicates stable data on the data bus.

AS

Address strobe. Asserted by the MASTER and indicate a stable address is present on the address lines.

BR0 through BR3

Bus request lines. MASTER request a busy bus via these prioritized levels.

BG0IN through BG3IN

Bus grant in (daisy-chained).

BG0OUT through BG3OUT

Bus grant out (daisy-chained).

BBSY

Busy busy.

BCLR

Bus clear. (Hint to bus master: VME MASTERs are not required to comply)

IRQ1 - IRQ7

Interrupt request lines.

IACK

Interrupt acknowledge. Asserted by MASTER to indicate the VME interrupt level to be serviced.

IACKIN

Interrupt acknowledge in (daisy-chained).

IACKOUT

Interrupt acknowledge out (daisy-chained.)

DTACK

Data transfer acknowledge. Asserted by SLAVE to indicate a successful bus transfer.

WRITE

Write not or read.

LWORD

Indicates long word transfer (D32).

SYSCLK

16 MHz system clock. (Does not control bus timing.)

SERCLK

Serial data clock.

SERDAT

Serial data line.

BERR

Bus error line.

SYSFAIL

Indicates a board has failed.

ACFAIL

AC power failure notify line.

SYSRESET

Reset signal for VME bus.


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Appendix D. Challenge IO4 PROM, Mezzanine, and Troubleshooting  Index